Re: AMD SEV-SNP/Intel TDX: validation of memory pages

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On 16/02/21 17:57, Andy Lutomirski wrote:


On Feb 16, 2021, at 7:59 AM, Paolo Bonzini <pbonzini@xxxxxxxxxx>
wrote:

On 16/02/21 15:46, Peter Zijlstra wrote:
On Tue, Feb 16, 2021 at 06:27:41AM -0800, Andi Kleen wrote: I
think the IST solution should at least be explored before dismissing it. It might be simpler than anything else (like using new APIs)
Have you seen the trainwreck bonzini proposed?

You had been suspiciously silent...

Can one of you point me at the original proposal?

https://lkml.org/lkml/2020/5/15/1239

(only pseudocode)

This sounds suspiciously like the current NMI code.

Yes, it's similar in concept. The exact circumstances of how nested #VE happens, however, are different from NMI, and the limitation of two nested #VEs simplifies things a bit.

I want to look at the code. If nothing else, I suspect it’s busted wrt CET,

Yes, that's the obvious part.  You'd have to add some WRSSP or whatnot.

Paolo

but the current NMI code definitely has bugs.  For example, if we are
about to IRET from NMI and we get #VE in the IRET insn itself and
then get a new NMI inside the #VE, we are toast.






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