i've been flipping through the source but haven't made much headway. the documentation doesn't really cover kbuild internals, so that didn't help. hopefully someone here can point me in the right direction. i'm interested in the exact make mechanics that kbuild utilizes to avoid make recursion (`make -C`) but while supporting its own include recursion. for example, fs/Makefile has lines like: obj-y += ramfs/ where is the logic that parses $(obj-y) and knows that it needs to recursively include ramfs/Makefile ? also, how are collisions avoided in variable names ? for example, kernel/Makefile has lines like: CFLAGS_REMOVE_irq_work.o = -pg how does kbuild know to apply this to building kernel/irq_work.o and not a irq_work.o object in any other dir ? -mike
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