On 11/16/2011 05:56 PM, Mark Brown wrote: > On Wed, Nov 16, 2011 at 05:52:49PM +0100, Lars-Peter Clausen wrote: >> On 11/16/2011 05:38 PM, Mark Brown wrote: > >>>> Hm? The use case here is chips which do not support readback. So we never >>>> want to fallback to a hardware read but still want to be able to do a cached >>>> read. > >>> This code will be run on every chip, including chips with read/write >>> access. Caches are useful for all chips. > >> Of course. And it still works for chips with read/write support with this >> patch, but it doesn't work for chips without read support without this patch. > > No, it'll fail if we ever cache volatile registers at startup (which > is a perfectly sensible thing to do for things like chip revisions - > they're not something we can hard code the default for but they're not > going to change at runtime). > Ah ok, now I get it, you are talking about that this will hypothetical break a future patch ;) >>> If you're looking at the read function and it's checking to see if the >>> register is writeable the first thought would be that this is a >>> cut'n'paste error. The above code is at best *way* too cute. > >> We can of course add a comment explaining why it is regmap_writable instead >> of regmap_readable. > > No, really - just do something legible and robust. For example, teach > regmap_readable() about the cache. Doesn't make much sense. We call regmap_readable from regcache_read, which is only called if we use a cache. So if we let regmap_readable return true in case we use a cache it will always be true in regcache_read and we can drop the check entirely. I'll update the patch to just drop the check. -- To unsubscribe from this list: send the line "unsubscribe linux-iio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
