On Wed, Nov 16, 2011 at 05:34:33PM +0100, Lars-Peter Clausen wrote: > On 11/16/2011 05:16 PM, Mark Brown wrote: > > This logic doesn't entirely follow - one can have registers which are > > volatile but could be read once at startup. Plus... > Hm? The use case here is chips which do not support readback. So we never > want to fallback to a hardware read but still want to be able to do a cached > read. This code will be run on every chip, including chips with read/write access. Caches are useful for all chips. > >> @@ -206,7 +206,7 @@ int regcache_read(struct regmap *map, > >> BUG_ON(!map->cache_ops); > >> - if (!regmap_readable(map, reg)) > >> + if (!regmap_writeable(map, reg)) > >> return -EIO; > > ...the code winds up just looking like an obvious bug. > Why? If a register is not writable we won't have anything in the cache for > it. So reading from the cache for a register which is not writable doesn't > make any sense. If you're looking at the read function and it's checking to see if the register is writeable the first thought would be that this is a cut'n'paste error. The above code is at best *way* too cute. -- To unsubscribe from this list: send the line "unsubscribe linux-iio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
