Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> writes: > On Mon, 2015-12-21 at 18:16 +0000, Måns Rullgård wrote: >> Andy Shevchenko <andy.shevchenko@xxxxxxxxx> writes: >> >> > On Mon, Dec 21, 2015 at 2:15 PM, Måns Rullgård <mans@xxxxxxxxx> >> > wrote: >> > > Andy Shevchenko <andy.shevchenko@xxxxxxxxx> writes: >> > > >> > I used to have a patch to implement this in dw_dmac driver. >> > However, I >> > dropped it at some point. Seems we need it back and now I possible >> > have a good explanation why. >> >> Are you still able to find that patch? Shouldn't be too hard to do >> from scratch if not. > > Yes, I found a version of it, let me mock up tomorrow something > working. > >> >> > > If those values didn't matter, why would the fields exist in the >> > > first place? >> > >> > Because someone can have more than one AHB bus on the system and >> > connect DMA to all of them (up to 4). >> >> Which apparently these guys did. Well, not a full-blown AHB bus, but >> they seem to be using two master interfaces. > > To different buses? Intel HW uses two masters and they are quite equal > (at least from OS point of view, it might be HW adjusts it). Judging by the block diagram in the 460EX datasheet [1], and by the fact that the old SATA driver works despite using an invalid address, the DMA FIFO of the controller isn't connected to the AHB bus at all but directly to master 0 on the DW DMA controller. Master 1 of the DMA controller is connected to the AHB bus, which is bridged to the main system bus. I haven't managed to find a full manual for the 460EX. [1] http://datasheet.octopart.com/PPC460EX-NUB800T-AMCC-datasheet-11553412.pdf -- Måns Rullgård -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
