On Tue, Mar 21 2006, Mark Lord wrote: > Mark Lord wrote: > >Jeff Garzik wrote: > >> > >>>In the case of sata_mv on the Marvell 6081 (which I'm looking at this > >>>week) > >>>it's hardware limit is actually 0xffffffff rather than 0xffff. > >> > >>If the limit is not 0xffff, then there's no need for any of this > >>limitation junk. No s/g entry splitting after pci_map_sg(), no > >>artificial sg_tablesize limitation, etc. > > > >Not even for a merged IOMMU segment that crosses the 4GB "boundary" ? > > Clarification: this is a 64-bit PCI(e/X) device, and the above query > applies mainly to it's use in a 64-bit slot on a 64-bit kernel. > > It's not clear to me whether this can be an issue on a 32-bit kernel > on 36-bit hardware, though. My explanation was for the block layer part of course, I'm hoping (did not check) that the iommu has similar sane defaults. But this still really wants a unification of the dma restrictions... -- Jens Axboe - : send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
