> > > /* Set the slave address in address register - triggers operation */ > > > cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, > > > CDNS_I2C_ADDR_OFFSET); > > > @@ -413,6 +415,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id) > > > ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && > > > (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) > > > cdns_i2c_clear_bus_hold(id); > > > + local_irq_restore(flags); > > > cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); > > > } > > > > > > > > > > Acked-by: Michal Simek <michal.simek@xxxxxxxxxx> > > What if another CPU core processes the interrupt handler? > The issue is that due to non i2c interrupts the clear is not released and the timeout is reached. If those interrupts are serviced on the other core should not be an issue.
