> >>Does that power down really disable reading from PCIe controller > >>registers or is it just PHY power down? > > > >I haven't experimented with it, but every block that has a clock gate > >has a power down, so I doubt it is just a phy power down. > > Ok, I see. But it isn't documented in the public FS, is it? If there is > an extra powerdown register for each ip block, I guess it will also > break reading from its registers. Hi Sebastian The public Kirkwood FS has a memory power management control register, Offset 0x20118. It is unclear what it actually does, and if you can still access registers when it is off. We would have to poke it and see. Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
