On Mon, 30 Apr 2007, e9hack wrote:
> I've some question to this patch:
>
> Trent Piepho wrote:
> > Include the patch this time
> > diff --git a/linux/drivers/media/dvb/frontends/dvb-pll.c b/linux/drivers/media/dvb/frontends/dvb-pll.c
> > --- a/linux/drivers/media/dvb/frontends/dvb-pll.c
> > +++ b/linux/drivers/media/dvb/frontends/dvb-pll.c
> > @@ -38,6 +38,12 @@
> > 0x50 = AGC Take over point = 103 dBuV */
> > static u8 tua603x_agc103[] = { 2, 0x80|0x40|0x18|0x06|0x01, 0x00|0x50 };
> >
> > +/* 0x04 = 166.67 kHz divider
> > +
> > + 0x80 = AGC Time constant 50ms Iagc = 9 uA
> > + 0x20 = AGC Take over point = 112 dBuV */
> > +static u8 tua603x_agc112[] = { 2, 0x80|0x40|0x18|0x04|0x01, 0x80|0x20 };
>
> Why is the AGC time constant set permanently to 50ms (short time)? Usually, the AGC time constant of the tuner is set to
> the short time during tuning only. After the pll lock + some time (ca. 100ms), the AGC time constant should be switched
> back to 2s (long time). If the time constant isn't changed during tuning, they should be set to the long time.
Is this so that the AGC circuit can quickly adjust to the input level of
the new channel, but then have less AGC created noise added later?
Anyway, the 50ms AGC time constant is what is recommended in the fmd1216me
datasheet. It explicitly says in DVB-T mode, ATC == 1. And this is what
the existing users of the fmd1216me have been using (those that set AGC).
Maybe for this tuner, the smaller time constant is better? Adding support
for changing AGC settings after tuning is an entirely new patch.
> > .setbw = fmd1216me_bw,
> > + .initdata = tua603x_agc112,
> > + .sleepdata = (u8[]){ 4, 0x9c, 0x60, 0x85, 0x54 },
>
> In sleep mode, the AGC shouldn't be set into high impedance mode. A
> better solution is to disable the AGC. 0x60 should be 0x70. In sleep
> mode, P0 and P1 must be set to 1. This means 0x54 should be 0x54|0x03.
> Why is the value of the band switch byte 0x54? Bits 5,6 and 7 aren't
> used.
This isn't exactly sleep mode. See the earlier thread in this list with
the other Hartmut. When the DVB driver closes, the frontend (not just
PLL!) is put into "analog mode" so that the v4l driver will work.
Port P4 appears to control the tda9887 analog demod chip. This is why bit
port bit 0x10 is set. It's also why 0x03 sleep mode isn't used; the PLL's
port must remain on.
Setting the AGC to high-Z is what the datasheet recommends for analog mode.
I guess there is some other AGC source (I think the tda9887 has an agc
output, maybe that is it?). Again, this is also an existing intentional
effect of code in saa7134 which this patch replaces.
Why is port bit 0x40 set? I don't know. All the existing code does this.
The fmd1216me datasheet doesn't say what that bit does. The TUA6034
datasheet indicates the bit is unused. Yet several different examples in
the fmd1216me datasheet explicitly set port bit 0x40. It's either A) has
an important yet undocumented function, or B) has no affect what-so-ever.
Either way, seems safest to just leave it.
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