I've some question to this patch:
Trent Piepho wrote:
> Include the patch this time
> diff --git a/linux/drivers/media/dvb/frontends/dvb-pll.c b/linux/drivers/media/dvb/frontends/dvb-pll.c
> --- a/linux/drivers/media/dvb/frontends/dvb-pll.c
> +++ b/linux/drivers/media/dvb/frontends/dvb-pll.c
> @@ -38,6 +38,12 @@
> 0x50 = AGC Take over point = 103 dBuV */
> static u8 tua603x_agc103[] = { 2, 0x80|0x40|0x18|0x06|0x01, 0x00|0x50 };
>
> +/* 0x04 = 166.67 kHz divider
> +
> + 0x80 = AGC Time constant 50ms Iagc = 9 uA
> + 0x20 = AGC Take over point = 112 dBuV */
> +static u8 tua603x_agc112[] = { 2, 0x80|0x40|0x18|0x04|0x01, 0x80|0x20 };
Why is the AGC time constant set permanently to 50ms (short time)? Usually, the AGC time constant of the tuner is set to
the short time during tuning only. After the pll lock + some time (ca. 100ms), the AGC time constant should be switched
back to 2s (long time). If the time constant isn't changed during tuning, they should be set to the long time.
> +
> struct dvb_pll_desc dvb_pll_thomson_dtt7579 = {
> .name = "Thomson dtt7579",
> .min = 177000000,
> @@ -282,6 +288,8 @@ struct dvb_pll_desc dvb_pll_fmd1216me =
> .max = 858000000,
> .iffreq= 36125000,
> .setbw = fmd1216me_bw,
> + .initdata = tua603x_agc112,
> + .sleepdata = (u8[]){ 4, 0x9c, 0x60, 0x85, 0x54 },
In sleep mode, the AGC shouldn't be set into high impedance mode. A better solution is to disable the AGC. 0x60 should
be 0x70. In sleep mode, P0 and P1 must be set to 1. This means 0x54 should be 0x54|0x03. Why is the value of the band
switch byte 0x54? Bits 5,6 and 7 aren't used.
- Hartmut
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