Hi Sergio,
On 4/6/19 5:59 am, Sergio Paracuellos wrote:
On Mon, Jun 3, 2019 at 2:32 PM Greg Ungerer <gerg@xxxxxxxxxx> wrote:
On 3/6/19 3:34 pm, Sergio Paracuellos wrote:
On Mon, Jun 3, 2019 at 3:26 AM Greg Ungerer <gerg@xxxxxxxxxx> wrote:
On 31/5/19 10:37 pm, Sergio Paracuellos wrote:
On Thu, May 30, 2019 at 3:46 AM Greg Ungerer <gerg@xxxxxxxxxx> wrote:
On 30/5/19 10:44 am, Greg Ungerer wrote:
On 29/5/19 6:08 pm, Sergio Paracuellos wrote:
[snip]
Can you try to read and set BIT(10) instead of write it directly?:
Instead of:
rt_sysc_w32(PERST_MODE_GPIO, MT7621_GPIO_MODE);
Oh, yeah, that is definitely not going to work. There is a bunch of
other GPIO control bits in there for other hardware blocks. Would
explain the broken NAND flash behavior...
Yes, my bad here. Sometimes is better to go to sleep :)).
Do:
u32 val = rt_sysc_r32(MT7621_GPIO_MODE);
val |= PERST_MODE_GPIO;
rt_sysc_w32(val, MT7621_GPIO_MODE);
Much better result with that. Though ultimately it should clear
bits 10 and 11 (both are PERST_MODE bits) and then OR in BIT(10).
Ok, so the following should do the trick:
rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
with PERST_MODE_MASK defined as:
#define PERST_MODE_MASK GENMASK(11, 10)
(patch attached with this changes)
I have mostly good news and a little bad news :-)
I should have tested more thoroughly last night. Anyway, the new patch
works, even the IRQ of the PCI device. My Wifi PCI device works just
as well now as it did with the 4.20 pci-mt7621.c/pci-mt7621-phy.c.
I still get the lines:
pcieport 0000:00:00.0: of_irq_parse_pci: failed with rc=-22
pcieport 0000:00:00.0: enabling device (0004 -> 0006)
However that is referring to the root host PCI device (0000:00:00.0),
not my PCI peripheral device (which is 0000:01:00.0). It is actually
probed and working properly.
That is the good news.
It would be also good to know what happen if you comment the following lines:
pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
Are they really needed?
Had no effect for me. Everything worked the same with or without
those lines as far as I could tell.
[snip]
Only one step more to get this properly working.
Ok, now the bad news.
I often get the boot hanging at various points in the PCI
initialization, setup and probing.
For example sometimes it hangs with boot up to:
mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
Then sometimes it hangs at:
mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
And then I also see it hang up to:
mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
mt7621-pci 1e140000.pcie: PCIE0 enabled
mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0xffffffff]
pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
pci_bus 0000:00: root bus resource [bus 00-ff]
pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
It happens on cold or warm boots. Sometimes it boots up all the
way and everything works perfectly.
I had perfect reliable boot and operation with linux-5.1 using the
older 4.20 pci-mt7621.c and pci-mt7621-phy.c.
Regards
Greg
_______________________________________________
devel mailing list
devel@xxxxxxxxxxxxxxxxxxxxxx
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
