Re: staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function

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Hi Sergio,

On 30/5/19 10:44 am, Greg Ungerer wrote:
On 29/5/19 6:08 pm, Sergio Paracuellos wrote:
[snip]
I have added gpio consumer stuff and reorder a bit the code to be more
similar to 4.20.

I attach the patch. I have not try it to compile it, because my normal
environment is in another
computer and I am in the middle of moving from my current house and
don't have access to it, sorry.
So, please try this and let's see what happens.

No problem, thanks for the patch.

Unfortunately always locks up on kernel boot:

   ...
   mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
   mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
   mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
   mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
   mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
   mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
   mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
   mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
   mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)

That was original linux-5.1 patched with your attached patch.

I'll try and dig down into that further today and get some
feedback on where it is failing.

The first problem I see is that the GPIO MODE register bits for
PERST_MODE are set to 00, so in "PCIe Reset" mode. If I hack in
a register update for that with:

    /* Force PERST PCIe reset into GPIO mode */
    *(unsigned int *)(0xbe000060) |=  BIT(10);

I do that at the start of mt7621_pcie_init_ports(). With that in
place I get further:

  mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
  mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
  mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
  mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
  mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
  mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
  mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
  mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
  mt7621-pci 1e140000.pcie: PCIE0 enabled
  mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
  mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
  pci_bus 0000:00: root bus resource [io  0xffffffff]
  pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
  pci_bus 0000:00: root bus resource [bus 00-ff]
  pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

It hangs there...

Regards
Greg


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