Hi Greg,
On Mon, Jun 3, 2019 at 2:32 PM Greg Ungerer <gerg@xxxxxxxxxx> wrote:
>
> Hi Sergio,
>
> On 3/6/19 3:34 pm, Sergio Paracuellos wrote:
> > On Mon, Jun 3, 2019 at 3:26 AM Greg Ungerer <gerg@xxxxxxxxxx> wrote:
> >> On 31/5/19 10:37 pm, Sergio Paracuellos wrote:
> >>> On Thu, May 30, 2019 at 3:46 AM Greg Ungerer <gerg@xxxxxxxxxx> wrote:
> >>>> On 30/5/19 10:44 am, Greg Ungerer wrote:
> >>>>> On 29/5/19 6:08 pm, Sergio Paracuellos wrote:
> >>>>> [snip]
> >>>>>> I have added gpio consumer stuff and reorder a bit the code to be more
> >>>>>> similar to 4.20.
> >>>>>>
> >>>>>> I attach the patch. I have not try it to compile it, because my normal
> >>>>>> environment is in another
> >>>>>> computer and I am in the middle of moving from my current house and
> >>>>>> don't have access to it, sorry.
> >>>>>> So, please try this and let's see what happens.
> >>>>>
> >>>>> No problem, thanks for the patch.
> >>>>>
> >>>>> Unfortunately always locks up on kernel boot:
> >>>>>
> >>>>> ...
> >>>>> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> >>>>> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
> >>>>> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> >>>>> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
> >>>>> mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
> >>>>> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
> >>>>> mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
> >>>>> mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
> >>>>> mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
> >>>>>
> >>>>> That was original linux-5.1 patched with your attached patch.
> >>>>>
> >>>>> I'll try and dig down into that further today and get some
> >>>>> feedback on where it is failing.
> >>>>
> >>>> The first problem I see is that the GPIO MODE register bits for
> >>>> PERST_MODE are set to 00, so in "PCIe Reset" mode. If I hack in
> >>>> a register update for that with:
> >>>>
> >>>> /* Force PERST PCIe reset into GPIO mode */
> >>>> *(unsigned int *)(0xbe000060) |= BIT(10);
> >>>
> >>> I have set GPIO mode for this in the new attached patch.
> >>>
> >>>>
> >>>> I do that at the start of mt7621_pcie_init_ports(). With that in
> >>>> place I get further:
> >>>>
> >>>> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> >>>> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
> >>>> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> >>>> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
> >>>> mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
> >>>> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
> >>>> mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
> >>>> mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
> >>>> mt7621-pci 1e140000.pcie: PCIE0 enabled
> >>>> mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
> >>>> mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> >>>> pci_bus 0000:00: root bus resource [io 0xffffffff]
> >>>> pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
> >>>> pci_bus 0000:00: root bus resource [bus 00-ff]
> >>>> pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> >>>>
> >>>> It hangs there...
> >>>
> >>> I had review the boot order is working for you in version 4.20 and the
> >>> order with the new patch applied. There were
> >>> only one difference, the place where interrupt bits are set. I have
> >>> changed that also in the new attached patch.
> >>>
> >>> For me, the order now and how the different boot steps are being done
> >>> in v4.20 are the same.
> >>>
> >>> One other thing I don't really understand why is needed but is in the
> >>> v4.20 code are this two lines:
> >>>
> >>> pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
> >>> pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
> >>>
> >>> These are added also in the current patch.
> >>
> >> Tried out this latest patch. Unfortunately no good news.
> >>
> >> Boot gets through the PCI bus scan, but does not find any devices:
> >>
> >> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> >> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
> >> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> >> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
> >> mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
> >> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
> >> mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
> >> mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
> >> mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
> >> mt7621-pci 1e140000.pcie: Nothing is connected in virtual bridges. Exiting...
> >
> >
> >
> >>
> >> And now in the completely weird and un-expected department the boot
> >> continues on and appears to hang for me when it tries to attach a
> >> UBI NAND flash partition. It hangs there for about a minute or so
> >> and then dumps complaing about flash problems:
> >>
> >> ubi0: attaching mtd3
> >> ubi0: scanning is finished
> >> ubi0: empty MTD device detected
> >> ubi0 warning: do_sync_erase: error -5 while erasing PEB 0, retry
> >> ubi0 warning: do_sync_erase: error -5 while erasing PEB 0, retry
> >> ubi0 warning: do_sync_erase: error -5 while erasing PEB 0, retry
> >> ubi0 error: do_sync_erase: cannot erase PEB 0, error -5
> >> CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.1.0-ac0 #59
> >> Stack : 000000f0 00000000 00000000 808e0000 8ebf2000 80070584 808285b8 0000000b
> >> 00000038 00000000 80827e00 8fc23b1c 80870000 00000001 8fc23ab0 aeddef9b
> >> 00000000 00000000 80920000 00000000 00000000 808e7693 000000f1 00000000
> >> 203a6d6d 00000000 00000000 00000000 80870000 00000000 00000000 8080a01c
> >> 00000000 80870000 8ebf1014 8ebd2000 00000018 80361d24 00000004 808e0004
> >> ...
> >> Call Trace:
> >> [<8000cfc0>] show_stack+0x94/0x12c
> >> [<806e553c>] dump_stack+0x8c/0xd0
> >> [<803c73c8>] do_sync_erase+0xf4/0x208
> >> [<803c7694>] ubi_io_sync_erase+0x1b8/0x304
> >> [<803cbc90>] ubi_early_get_peb+0x148/0x1dc
> >> [<803ba930>] create_vtbl+0xb4/0x29c
> >> [<803bafc8>] ubi_read_volume_table+0x27c/0xae4
> >> [<803cc294>] ubi_attach+0x570/0x15dc
> >> [<803bf2a0>] ubi_attach_mtd_dev+0x5b0/0xbec
> >> [<808b0488>] ubi_init+0x1c0/0x274
> >> [<800015f4>] do_one_initcall+0x50/0x1ac
> >> [<80897e98>] kernel_init_freeable+0x184/0x26c
> >> [<807035b4>] kernel_init+0x14/0x110
> >> [<800071f8>] ret_from_kernel_thread+0x14/0x1c
> >>
> >> I tried booting and running this several times, I always get the same
> >> long hang and dump from USB/NAND. If I copy in the one linux-4.20
> >> file, drivers/staging/mt7621-pci/pci-mt7621.c, then the system
> >> boots, scans and finds PCI devices, and does not hang/dump on
> >> UBI/NAND flash setup.
> >
> > Can you try to read and set BIT(10) instead of write it directly?:
> >
> > Instead of:
> >
> > rt_sysc_w32(PERST_MODE_GPIO, MT7621_GPIO_MODE);
>
> Oh, yeah, that is definitely not going to work. There is a bunch of
> other GPIO control bits in there for other hardware blocks. Would
> explain the broken NAND flash behavior...
Yes, my bad here. Sometimes is better to go to sleep :)).
>
>
> > Do:
> >
> > u32 val = rt_sysc_r32(MT7621_GPIO_MODE);
> > val |= PERST_MODE_GPIO;
> > rt_sysc_w32(val, MT7621_GPIO_MODE);
>
> Much better result with that. Though ultimately it should clear
> bits 10 and 11 (both are PERST_MODE bits) and then OR in BIT(10).
Ok, so the following should do the trick:
rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
with PERST_MODE_MASK defined as:
#define PERST_MODE_MASK GENMASK(11, 10)
(patch attached with this changes)
It would be also good to know what happen if you comment the following lines:
pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
Are they really needed?
>
> Boot is successful and now shows:
>
> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
> mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
> mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
> mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
> mt7621-pci 1e140000.pcie: PCIE0 enabled
> mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
> mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> pci_bus 0000:00: root bus resource [io 0xffffffff]
> pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
> pci_bus 0000:00: root bus resource [bus 00-ff]
> pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
> pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
> pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x601fffff]
> pci 0000:00:00.0: BAR 9: assigned [mem 0x60200000-0x602fffff pref]
> pci 0000:00:00.0: BAR 1: assigned [mem 0x60300000-0x6030ffff]
> pci 0000:00:00.0: BAR 7: no space for [io size 0x1000]
> pci 0000:00:00.0: BAR 7: failed to assign [io size 0x1000]
> pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x601fffff 64bit]
> pci 0000:01:00.0: BAR 6: assigned [mem 0x60200000-0x6020ffff pref]
> pci 0000:00:00.0: PCI bridge to [bus 01]
> pci 0000:00:00.0: bridge window [mem 0x60000000-0x601fffff]
> pci 0000:00:00.0: bridge window [mem 0x60200000-0x602fffff pref]
> pcieport 0000:00:00.0: of_irq_parse_pci: failed with rc=-22
> pcieport 0000:00:00.0: enabling device (0004 -> 0006)
>
>
> So that is really good. Still now just some problem with the IRQ.
No idea at all why irq is failing there. The driver code related with
irq is the same for 4.20.
Some debug traces would be useful.
>
> I also found that I could dump /sys/bus/pci/devices/0000:01:00.0/config
> and get a good dump from the command line:
>
> 00000000: 8c 16 3c 00 06 00 10 00 00 00 80 02 00 00 00 00 ..<.............
> 00000010: 04 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 ...`............
> 00000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
> 00000030: 00 00 00 00 40 00 00 00 00 00 00 00 17 01 00 00 ....@...........
> ...
>
> Also good.
Yeah, That looks good. Much better than getting all F's like the other day.
>
>
> >> I'll try and dig into it some time today and get you some feedback.
>
> Sorry, I didn't get any more time to look at this today.
>
No problem at all.
>
> > No other changes with the previous one, just the order of where
> > interrupts bits are set up in
> > the same place of 4.20.
> >
> > Can you point me out to the link to your board of something to check
> > if I can acquire one and test
> > in my side?
>
> I am using a Digi/EX15:
> https://www.digi.com/products/networking/cellular-routers/enterprise/digi-ex15
>
> FWIW, I think we are close now.
Only one step more to get this properly working.
>
> Regards
> Greg
Best regards,
Sergio Paracuellos
From cb33266157579ecaa720e6b8385b972264f999f6 Mon Sep 17 00:00:00 2001
From: Sergio Paracuellos <sparacuellos@xxxxxxxxxxxx>
Date: Wed, 29 May 2019 09:58:07 +0200
Subject: [PATCH] staging: mt7621-pci: use perst gpio instead of builtin perst
Some boards need gpio instead of builtin perst. Use gpio for all
of them which was the approach of the original code.
Signed-off-by: Sergio Paracuellos <sparacuellos@xxxxxxxxxxxx>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 3 +-
drivers/staging/mt7621-pci/pci-mt7621.c | 114 +++++++++++++++++---------------
2 files changed, 62 insertions(+), 55 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 280ec33..aed2458 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,5 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
-
+#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -468,6 +468,7 @@
#address-cells = <3>;
#size-cells = <2>;
+ perst-gpio = <&gpio 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 03d919a..9ff4a8f 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -17,6 +17,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -35,6 +36,7 @@
/* sysctl */
#define MT7621_CHIP_REV_ID 0x0c
+#define MT7621_GPIO_MODE 0x60
#define CHIP_REV_MT7621_E2 0x0101
/* MediaTek specific configuration registers */
@@ -75,13 +77,13 @@
#define RALINK_PCI_STATUS 0x0050
/* Some definition values */
+#define RALINK_PCI_IO_MAP_BASE 0x1e160000
#define PCIE_REVISION_ID BIT(0)
#define PCIE_CLASS_CODE (0x60400 << 8)
#define PCIE_BAR_MAP_MAX GENMASK(30, 16)
#define PCIE_BAR_ENABLE BIT(0)
#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
#define PCIE_PORT_CLK_EN(x) BIT(24 + (x))
-#define PCIE_PORT_PERST(x) BIT(1 + (x))
#define PCIE_PORT_LINKUP BIT(0)
#define PCIE_CLK_GEN_EN BIT(31)
@@ -90,6 +92,10 @@
#define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25))
#define MEMORY_BASE 0x0
+#define PERST_MODE_MASK GENMASK(11, 10)
+#define PERST_MODE_GPIO BIT(10)
+#define PERST_DELAY_US 1000
+
/**
* struct mt7621_pcie_port - PCIe port information
* @base: I/O mapped register base
@@ -119,6 +125,7 @@ struct mt7621_pcie_port {
* @offset: IO / Memory offset
* @dev: Pointer to PCIe device
* @ports: pointer to PCIe port information
+ * @perst: gpio reset
* @rst: pointer to pcie reset
*/
struct mt7621_pcie {
@@ -132,6 +139,7 @@ struct mt7621_pcie {
resource_size_t io;
} offset;
struct list_head ports;
+ struct gpio_desc *perst;
struct reset_control *rst;
};
@@ -198,6 +206,18 @@ static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
+static void mt7621_perst_gpio_pcie_assert(struct mt7621_pcie *pcie)
+{
+ gpiod_set_value(pcie->perst, 0);
+ mdelay(PERST_DELAY_US);
+}
+
+static void mt7621_perst_gpio_pcie_deassert(struct mt7621_pcie *pcie)
+{
+ gpiod_set_value(pcie->perst, 1);
+ mdelay(PERST_DELAY_US);
+}
+
static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
{
u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
@@ -344,6 +364,12 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
struct resource regs;
int err;
+ pcie->perst = devm_gpiod_get(dev, "perst", GPIOD_OUT_HIGH);
+ if (IS_ERR(pcie->perst)) {
+ dev_err(dev, "failed to get gpio perst\n");
+ return PTR_ERR(pcie->perst);
+ }
+
err = of_address_to_resource(node, 0, ®s);
if (err) {
dev_err(dev, "missing \"reg\" property\n");
@@ -384,7 +410,6 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
struct mt7621_pcie *pcie = port->pcie;
struct device *dev = pcie->dev;
u32 slot = port->slot;
- u32 val = 0;
int err;
/*
@@ -393,47 +418,33 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
*/
mt7621_reset_port(port);
- val = read_config(pcie, slot, PCIE_FTS_NUM);
- dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
-
err = phy_init(port->phy);
if (err) {
dev_err(dev, "failed to initialize port%d phy\n", slot);
- goto err_phy_init;
+ return err;
}
err = phy_power_on(port->phy);
if (err) {
dev_err(dev, "failed to power on port%d phy\n", slot);
- goto err_phy_on;
- }
-
- if ((pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) == 0) {
- dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
- mt7621_control_assert(port);
- port->enabled = false;
- err = -ENODEV;
- goto err_no_link_up;
+ return err;
}
port->enabled = true;
return 0;
-
-err_no_link_up:
- phy_power_off(port->phy);
-err_phy_on:
- phy_exit(port->phy);
-err_phy_init:
- return err;
}
static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
{
struct device *dev = pcie->dev;
struct mt7621_pcie_port *port, *tmp;
+ u32 val = 0;
int err;
+ rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
+ mt7621_perst_gpio_pcie_assert(pcie);
+
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
u32 slot = port->slot;
@@ -441,7 +452,10 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
if (err) {
dev_err(dev, "Initiating port %d failed\n", slot);
list_del(&port->list);
- }
+ } else {
+ val = read_config(pcie, slot, PCIE_FTS_NUM);
+ dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
+ }
}
reset_control_assert(pcie->rst);
@@ -451,37 +465,32 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
msleep(50);
reset_control_deassert(pcie->rst);
+
+ mt7621_perst_gpio_pcie_deassert(pcie);
+
+ list_for_each_entry(port, &pcie->ports, list) {
+ u32 slot = port->slot;
+
+ if ((pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) == 0) {
+ dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
+ mt7621_control_assert(port);
+ phy_power_off(port->phy);
+ port->enabled = false;
+ } else {
+ /* enable pcie interrupt */
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= PCIE_PORT_INT_EN(slot);
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
+ }
+ }
}
-static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
+static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
{
struct mt7621_pcie *pcie = port->pcie;
u32 slot = port->slot;
u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
u32 val;
- int err;
-
- /* assert port PERST_N */
- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
- val |= PCIE_PORT_PERST(slot);
- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
-
- /* de-assert port PERST_N */
- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
- val &= ~PCIE_PORT_PERST(slot);
- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
-
- /* 100ms timeout value should be enough for Gen1 training */
- err = readl_poll_timeout(port->base + RALINK_PCI_STATUS,
- val, !!(val & PCIE_PORT_LINKUP),
- 20, 100 * USEC_PER_MSEC);
- if (err)
- return -ETIMEDOUT;
-
- /* enable pcie interrupt */
- val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
- val |= PCIE_PORT_INT_EN(slot);
- pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
/* map 2G DDR region */
pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
@@ -492,8 +501,6 @@ static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
/* configure class code and revision ID */
pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
offset + RALINK_PCI_CLASS);
-
- return 0;
}
static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
@@ -506,11 +513,7 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
list_for_each_entry(port, &pcie->ports, list) {
if (port->enabled) {
- if (mt7621_pcie_enable_port(port)) {
- dev_err(dev, "de-assert port %d PERST_N\n",
- port->slot);
- continue;
- }
+ mt7621_pcie_enable_port(port);
dev_info(dev, "PCIE%d enabled\n", slot);
num_slots_enabled++;
}
@@ -665,6 +668,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
return 0;
}
+ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
+ pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
+
mt7621_pcie_enable_ports(pcie);
err = mt7621_pci_parse_request_of_pci_ranges(pcie);
--
2.7.4
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