Re: [PATCH 6/7] dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY

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On Wed, Jan 31, 2018 at 11:29 PM, Archit Taneja <architt@xxxxxxxxxxxxxx> wrote:
>
>
> On 01/31/2018 09:50 PM, Rob Clark wrote:
>>
>> On Wed, Jan 31, 2018 at 1:40 AM, Archit Taneja <architt@xxxxxxxxxxxxxx>
>> wrote:
>>>
>>>
>>>
>>> On 01/29/2018 10:45 PM, Rob Herring wrote:
>>>>
>>>>
>>>> On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote:
>>>>>
>>>>>
>>>>> Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
>>>>>   From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not
>>>>> required,
>>>>> but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names
>>>>> each PHY revision needs.
>>>>>
>>>>> Cc: Rob Herring <robh@xxxxxxxxxx>
>>>>> Cc: devicetree@xxxxxxxxxxxxxxx
>>>>> Signed-off-by: Archit Taneja <architt@xxxxxxxxxxxxxx>
>>>>> ---
>>>>>    Documentation/devicetree/bindings/display/msm/dsi.txt | 13
>>>>> +++++++++++--
>>>>>    1 file changed, 11 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt
>>>>> b/Documentation/devicetree/bindings/display/msm/dsi.txt
>>>>> index 9c3ad6bbb9f0..26a1796b7145 100644
>>>>> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt
>>>>> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
>>>>> @@ -86,12 +86,19 @@ Required properties:
>>>>>      * "qcom,dsi-phy-28nm-lp"
>>>>>      * "qcom,dsi-phy-20nm"
>>>>>      * "qcom,dsi-phy-28nm-8960"
>>>>> -- reg: Physical base address and length of the registers of PLL, PHY
>>>>> and
>>>>> PHY
>>>>> -  regulator
>>>>> +  * "qcom,dsi-phy-14nm"
>>>>> +- reg: Physical base address and length of the registers of PLL, PHY.
>>>>> Some
>>>>> +  revisions require the PHY regulator base address, whereas others
>>>>> require the
>>>>> +  PHY lane base address. See below for each PHY revision.
>>>>>    - reg-names: The names of register regions. The following regions
>>>>> are
>>>>> required:
>>>>> +  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
>>>>>      * "dsi_pll"
>>>>>      * "dsi_phy"
>>>>>      * "dsi_phy_regulator"
>>>>> +  For DSI 14nm PHY:
>>>>> +  * "dsi_pll"
>>>>> +  * "dsi_phy"
>>>>> +  * "dsi_phy_lane"
>>>>>    - clock-cells: Must be 1. The DSI PHY block acts as a clock
>>>>> provider,
>>>>> creating
>>>>>      2 clocks: A byte clock (index 0), and a pixel clock (index 1).
>>>>>    - power-domains: Should be <&mmcc MDSS_GDSC>.
>>>>> @@ -102,6 +109,8 @@ Required properties:
>>>>>    - vddio-supply: phandle to vdd-io regulator device node
>>>>>      For 20nm PHY:
>>>>>    - vddio-supply: phandle to vdd-io regulator device node
>>>>> +- vcca-supply: phandle to vcca regulator device node
>>>>
>>>>
>>>>
>>>> Did you mean to add this?
>>>
>>>
>>>
>>> Yes, I didn't intend it to be a part of this patch, but this supply is
>>> indeed needed for the
>>> 20nm PHY. I'll move this to a separate patch.
>>
>>
>> actually, this looks correct, just formatted counter-intuitively by
>> git-format-patch..
>>
>> vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi:
>> Fix the PHY regulator supply props", but when 14nm phy is added in
>> this patch, it shows the addition of same line beneath 14nm PHY as an
>> addition above the line.
>>
>> So I don't think it needs to be split up.
>
>
> Oh yeah, you're right. I guess this is okay as is, then.

Doh!

Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
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