On Tue, Jul 02, 2024 at 09:20:40PM GMT, Satya Priya Kakitapalli wrote: > The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha > value is greater than 0.5, the L value needs to be adjusted accordingly. > Thus update the logic for the same. > > Also, fix zonda set_rate failure when PLL is disabled. Currently, > clk_zonda_pll_set_rate polls for the PLL to lock even if the PLL is > disabled. However, if the PLL is disabled then LOCK_DET will never > assert and we'll return an error. There is no reason to poll LOCK_DET > if the PLL is already disabled, so skip polling in this case. Two separate commits, missing Fixes tags. > > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@xxxxxxxxxxx> > --- > drivers/clk/qcom/clk-alpha-pll.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) -- With best wishes Dmitry
