On Thu, Feb 25, 2016 at 9:30 PM, Archit Taneja <architt@xxxxxxxxxxxxxx> wrote: > The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading > its current value from the NS register. > > Using the pre-divider wasn't really intended when creating these ops. > The pixel RCG was only intended to achieve fractional multiplication > provided in the pixel_table array. Leaving the pre-divider to the > existing register value results in a wrong pixel clock when the > bootloader sets up the display. This was left unidentified because > the IFC6410 Plus board on which this was verified didn't have a > bootloader that configured the display. > > Don't set the RCG pre-divider in freq_tbl to the existing NS register > value. Instead, set it based on the fractional multiplication we want. > Prevent using M/N counter when we can just manage with using the > pre-divider. > > Cc: John Stultz <john.stultz@xxxxxxxxxx> > Cc: Vinay Simha <vinaysimha@xxxxxxxxxxxxxxxxxxxx> > Signed-off-by: Archit Taneja <architt@xxxxxxxxxxxxxx> > --- > John, Vinay, could you please test this on N7 and confirm if it works? Hey Archit, So this did not work for me. I removed the earlier patch forcing pre_div to 1, and added this, but that ended up with a mostly black screen with a bit of blue slowly scrolling down the side. With the f.pre_div=1 line re-added, I don't see anything. The screen just goes black and doesn't come back. Let me know if I can test anything else for you, or add any debug messages. thanks -john -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
