On 1/12/2024 12:30 AM, Andrew Lunn wrote:
Sorry for the confusion, the pin nodes are for the MDIO and MDC, these
PINs are used by the dedicated hardware MDIO block in the SoC. I will update
the node name from mux_0 to MDC, mux_1 to MDIO, to make it clear. The driver
for this node is drivers/net/mdio/mdio-ipq4019.c, it is not related to the
mdio-mux-* code.
So these is all about pinmux.
Yes, it is about pinmux.
When you say:
PINs are used by the dedicated hardware MDIO block in the SoC
do you actually mean:
PINs are used by the two dedicated hardware MDIO blocks in the SoC.
You have two sets of mdio/mdc configurations here, so i assume there
are two MDIO hardware blocks, each being an MDIO bus master.
Andrew
There are two MDIO hardware blocks on IPQ5332 SoC. One is
for the MDIO bus master(gpio27, 28), which is for accessing the MDIO
slave devices(like PHY device). The mdio-ipq4019.c driver enables
this MDIO bus master.
Another one is the MDIO slave(gpio25, 26), which is dedicated
for receiving the back pressure signal from the connected Ethernet
switch device QCA8386.
There is a MDIO master block integrated in QCA8386 switch device, this
integrated MDIO master is dedicated for generating the back
pressure signal to IPQ5332 SoC.
This MDIO slave block of IPQ5322 just needs to configure these PIN
mux for MDC and MDIO PINs. No additional driver is needed for this MDIO
slave block of IPQ5332.
