Add the MDIO device tree of ipq5332.
Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 44 +++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index bc89480820cb..e6c780e69d6e 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -214,6 +214,38 @@ serial_0_pins: serial0-state {
drive-strength = <8>;
bias-pull-up;
};
+
+ mdio0_pins: mdio0-state {
+ mux_0 {
+ pins = "gpio25";
+ function = "mdc0";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ mux_1 {
+ pins = "gpio26";
+ function = "mdio0";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ mdio1_pins: mdio1-state {
+ mux_0 {
+ pins = "gpio27";
+ function = "mdc1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ mux_1 {
+ pins = "gpio28";
+ function = "mdio1";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
};
gcc: clock-controller@1800000 {
@@ -863,6 +895,18 @@ group0 {
};
};
};
+
+ mdio: mdio@90000 {
+ compatible = "qcom,ipq4019-mdio";
+ reg = <0x90000 0x64>;
+ pinctrl-0 = <&mdio1_pins &mdio0_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
+ clock-names = "gcc_mdio_ahb_clk";
+ status = "disabled";
+ };
};
timer {
--
2.42.0
