On 05/07/2012 05:47 PM, Raghavendra K T wrote: >> Not good. Solving a problem in software that is already solved by >> hardware? It's okay if there are no costs involved, but here we're >> introducing a new ABI that we'll have to maintain for a long time. >> > > > Hmm agree that being a step ahead of mighty hardware (and just an > improvement of 1-3%) is no good for long term (where PLE is future). > PLE is the present, not the future. It was introduced on later Nehalems and is present on all Westmeres. Two more processor generations have passed meanwhile. The AMD equivalent was also introduced around that timeframe. > Having said that, it is hard for me to resist saying : > bottleneck is somewhere else on PLE m/c and IMHO answer would be > combination of paravirt-spinlock + pv-flush-tb. > > But I need to come up with good number to argue in favour of the claim. > > PS: Nikunj had experimented that pv-flush tlb + paravirt-spinlock is a > win on PLE where only one of them alone could not prove the benefit. > I'd like to see those numbers, then. Ingo, please hold on the kvm-specific patches, meanwhile. -- error compiling committee.c: too many arguments to function -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
