On Wed, Nov 24, 2010 at 10:56:15AM -0600, Anthony Liguori wrote: > On 11/24/2010 10:48 AM, Gleb Natapov wrote: > >>They *aren't* ISA devices. Look at the PIIX3 spec. All of the > >>ports for these devices are positively decoded and not sent over the > >>ISA bus. > >> > >Over the external ISA bus you mean? > > There is no internal ISA bus. The reality is that the PIIX3 is a > microcontroller and most of the platform devices are probably > written in microcode. That's certainly the case with modern SuperIO > chips. > Qemu also does not have ISA bus. It has code that emulates ISA bus. It is not important how legacy functionality is implemented as long as it is compliant to legacy specification. > Very specifically, the PIIX3 has a white list of addresses that when > it sees the a PCI bus transaction for those addresses, it asserts > DEVSEL# and then routes the request to the write part of the chip to > handle it. For unhandled transactions, it then forwards them to the > ISA bus. > Yeah. In other words it serves some ISA transactions internally and others forward to external bus. -- Gleb. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
