2018-05-11 23:25 GMT+08:00 Sean Christopherson <sean.j.christopherson@xxxxxxxxx>: > On Thu, Apr 05, 2018 at 07:25:15PM +0000, Christopherson, Sean J wrote: >> On Thu, 2018-04-05, Jim Mattson wrote: >> > The sentence I quoted from the SDM is unequivocal. Are you saying that >> > this is an error in the SDM, and that it should actually read: >> > >> > A write to the LVT Timer Register that changes the timer mode *to >> > TSC-Deadline mode* disarms the local APIC timer. >> > >> > Has anyone reported this error to Intel, so that the manual can be corrected? >> >> I suspect that Wanpeng's analysis is correct and that the timer is >> disarmed only when changing to/from deadline mode, i.e. this is an >> SDM bug. I'll hunt down the actual behavior and report back (and >> file an SDM bug if that's indeed the issue). > > Confirmed SDM bug, the timer is only disarmed when switching between > TSC-Deadline and other modes. Great, as expected, thanks Christopherson! Regards, Wanpeng Li
