On Thu, Sep 28, 2017 at 6:06 PM, Wanpeng Li <kernellwp@xxxxxxxxx> wrote: > From: Wanpeng Li <wanpeng.li@xxxxxxxxxxx> > + /* > + * After the change of mode, the counter should not be reset and continue > + * counting down from where it was > + */ This seems to contradict the Intel SDM, volume 3, section 10.5.4.1: A write to the LVT Timer Register that changes the timer mode disarms the local APIC timer.
