On Thu, 2018-04-05, Jim Mattson wrote:
> The sentence I quoted from the SDM is unequivocal. Are you saying that
> this is an error in the SDM, and that it should actually read:
>
> A write to the LVT Timer Register that changes the timer mode *to
> TSC-Deadline mode* disarms the local APIC timer.
>
> Has anyone reported this error to Intel, so that the manual can be corrected?
I suspect that Wanpeng's analysis is correct and that the timer is
disarmed only when changing to/from deadline mode, i.e. this is an
SDM bug. I'll hunt down the actual behavior and report back (and
file an SDM bug if that's indeed the issue).
I have a copy of the SDM circa 2010, before deadline mode was added,
and there is no mention of the timer being disarmed when transitioning
between one-shot and periodic. And further down in 10.5.4.1 of the
current SDM, it has a second blurb about disarming the timer when
switching between TSC-deadline mode and other timer modes, which seems
to imply that switching between one-shot and periodic does not disarm
the timer.
In TSC-deadline mode, writing 0 to the IA32_TSC_DEADLINE MSR
disarms the local-APIC timer. Transitioning between TSC-deadline
mode and other timer modes also disarms the timer.
> On Wed, Apr 4, 2018 at 5:33 PM, Wanpeng Li <kernellwp@xxxxxxxxx> wrote:
> > 2018-04-05 8:25 GMT+08:00 Marc Orr <marcorr@xxxxxxxxxx>:
> >> I agree that the manual is confusing in that it makes the statement under
> >> the subsection about the TSC-Deadline mode. But the statement is also used
> >> to introduce Table 10-2, which discusses all three APIC timer modes (i.e.,
> >> One-shot, Periodic, and TSC-Deadline).
> >>
> >> Regardless, I found that this test fails on my system. When I dug into it,
> >> in addition to observing what the manual says, I also observed that in the
> >> KVM source code, the timer is armed when the APIC_TMICTT is written, whereas
> >> it is NOT armed when the APIC_LVTT register is written to change the APIC
> >> timer's mode.
> >
> > Xen guys verify on the bare-metal, the statement just influences
> > TSC-Deadline mode. Then, both Xen and KVM rework the lapic timer
> > emulation logic to behave more like real-hardware.
> >
> > Regards,
> > Wanpeng Li
