The sentence I quoted from the SDM is unequivocal. Are you saying that this is an error in the SDM, and that it should actually read: A write to the LVT Timer Register that changes the timer mode *to TSC-Deadline mode* disarms the local APIC timer. Has anyone reported this error to Intel, so that the manual can be corrected? On Wed, Apr 4, 2018 at 5:33 PM, Wanpeng Li <kernellwp@xxxxxxxxx> wrote: > 2018-04-05 8:25 GMT+08:00 Marc Orr <marcorr@xxxxxxxxxx>: >> I agree that the manual is confusing in that it makes the statement under >> the subsection about the TSC-Deadline mode. But the statement is also used >> to introduce Table 10-2, which discusses all three APIC timer modes (i.e., >> One-shot, Periodic, and TSC-Deadline). >> >> Regardless, I found that this test fails on my system. When I dug into it, >> in addition to observing what the manual says, I also observed that in the >> KVM source code, the timer is armed when the APIC_TMICTT is written, whereas >> it is NOT armed when the APIC_LVTT register is written to change the APIC >> timer's mode. > > Xen guys verify on the bare-metal, the statement just influences > TSC-Deadline mode. Then, both Xen and KVM rework the lapic timer > emulation logic to behave more like real-hardware. > > Regards, > Wanpeng Li
