Avi Kivity wrote:
> Dong, Eddie wrote:
>> OK.
>> Also back to Gleb's question, the reason I want to do that is to
>> simplify event
>> generation mechanism in current KVM.
>>
>> Today KVM use additional layer of exception/nmi/interrupt such as
>> vcpu.arch.exception.pending, vcpu->arch.interrupt.pending &
>> vcpu->arch.nmi_injected.
>> All those additional layer is due to compete of
>> VM_ENTRY_INTR_INFO_FIELD
>> write to inject the event. Both SVM & VMX has only one resource to
>> inject the virtual event but KVM generates 3 catagory of events in
>> parallel which further requires additional
>> logic to dictate among them.
>
> I thought of using a queue to hold all pending events (in a common
> format), sort it by priority, and inject the head.
The SDM Table 5-4 requires to merge 2 events together, i.e. convert to #DF/
Triple fault or inject serially when 2 events happens no matter NMI, IRQ or exception.
As if considering above events merging activity, that is a single element queue.
We could have either: 1) A pure SW "queue" that will be flush to HW
register later (VM_ENTRY_INTR_INFO_FIELD), 2) Direct use HW register.
A potential benefit is that it can avoid duplicated code and potential bugs
in current code as following patch shows if I understand correctly:
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2599,7 +2599,7 @@ static int handle_exception(struct kvm_vcpu *vcpu, struct
kvm_run *kvm_run)
cr2 = vmcs_readl(EXIT_QUALIFICATION);
KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
(u32)((u64)cr2 >> 32), handler);
- if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending
)
+ if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending
|| vcpu->arch.nmi_injected)
kvm_mmu_unprotect_page_virt(vcpu, cr2);
return kvm_mmu_page_fault(vcpu, cr2, error_code);
}
If using above merged SW "queue" or HW direct register, we can do like following:
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2599,7 +2599,7 @@ static int handle_exception(struct kvm_vcpu *vcpu, struct
kvm_run *kvm_run)
cr2 = vmcs_readl(EXIT_QUALIFICATION);
KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
(u32)((u64)cr2 >> 32), handler);
- if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending
)
+ if (vmcs_read(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK)
kvm_mmu_unprotect_page_virt(vcpu, cr2);
return kvm_mmu_page_fault(vcpu, cr2, error_code);
}
Either way are OK and up to you. BTW Xen uses HW register directly to representing
an pending event.
>
>> One example is that exception has higher priority
>> than NMI/IRQ injection in current code which is not true in reality.
>>
>
> I don't think it matters in practice, since the guest will see it as a
> timing issue. NMIs and IRQs are asynchronous (even those generated by
> the guest through the local APIC).
Yes. But also cause IRQ injection be delayed which may have side effect.
For example if guest exception handler is very longer or if guest VCPU fall into
recursive #GP. Within current logic, a guest IRQ event from KDB (IPI) running
on VCPU0, as an example, can't force the dead loop VCPU1 into KDB since it
is recursively #GP.
>
>> Another issue is that an failed event from previous injection say
>> IRQ or NMI may be discarded if an virtual exception happens in the
>> EXIT handling now. With the patch of generic double fault handling,
>> this case should be handled as normally.
>>
>
> Discarding an exception is usually okay as it will be regenerated. I
> don't think we discard interrupts or NMIs.
In reality (Running OS in guest), it doesn't happen so far. But architecturally,
it could. For example KVM injects an IRQ, but VM Resume get #PF and
back to KVM with IDT_VECTORING valid. Then KVM will put back the failed
IRQ to interrupt queue. But if #PF handling generates another exception,
then the interrupt queue won't be able to be injected, since KVM inject
exception first. And the interrupt queue is discarded at next VM Exit.
Overal, I think this is mostly for simplification but may benefit future
a lot. Especially with Gleb's recent cleanup, it soulds to be much easier to
do than before.
I may make mistake here, will like to see more comments.
thx, eddie
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