On 10/29/2015 12:25 PM, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Rather than looking at crtc->mode (which is the user mode) dig up the
> sync polarity settings from the adjusted_mode when programming
> TRANS_DP_CTL on CPT/PPT.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d3cd177..99fb33f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4170,6 +4170,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
> /* For PCH DP, enable TRANS_DP_CTL */
> if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
> + const struct drm_display_mode *adjusted_mode =
> + &intel_crtc->config->base.adjusted_mode;
> u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> reg = TRANS_DP_CTL(pipe);
> temp = I915_READ(reg);
> @@ -4179,9 +4181,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> temp |= TRANS_DP_OUTPUT_ENABLE;
> temp |= bpc << 9; /* same format but at 11:9 */
>
> - if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
> - if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
>
> switch (intel_trans_dp_port_sel(crtc)) {
>
God I wish we'd rename these structs a bit... "adjusted" and
"crtc->mode" don't really communicate much.
Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
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