From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
This series eliminates all spurious PCH FIFO underrun reports on my
machines during a BAT run ('-t basic -x reload -x suspend' actually).
It also eliminates the non-spurious but expected underrun reports
on ILK.
I also embarked on a small scale cleanup of the CPU eDP PLL code while
I was trying to get to the bottom of the underruns on ILK. So I figured
I'd include that work here as well.
I've tested this on ILK, SNB, two IVBs, and one HSW, with as many
displays plugged in as possible. What I could actually test is HSW/BDW
CRT output since I have no machine for that.
The series is available here:
git://github.com/vsyrjala/linux.git pch_fifo_underrun_fix_4
Ville Syrjälä (14):
drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe
config around
drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL
drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB
drm/i915: Enable PCH FIFO underruns later on HSW+
drm/i915: Re-enable PCH FIO underrun reporting after pipe has been
disabled
drm/i915: Check for FIFO underruns after modeset on IVB/HSW and
CPT/PPT
drm/i915: Check for CPT and not !IBX in
ironlake_disable_pch_transcoder()
drm/i915: Disable FIFO underrun reporting around IBX transcoder B
workaround
drm/i915: Hide underruns from eDP PLL and port enable on ILK
drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/
drm/i915: Remove ILK-A eDP PLL workaround notes
drm/i915: Clean up eDP PLL state asserts
drm/i915: Use intel_dp->DP in eDP PLL setup
drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on()
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 64 +++++++----
drivers/gpu/drm/i915/intel_dp.c | 179 ++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_drv.h | 12 +-
drivers/gpu/drm/i915/intel_fifo_underrun.c | 121 +++++++++++++++----
drivers/gpu/drm/i915/intel_hdmi.c | 11 ++
drivers/gpu/drm/i915/intel_sdvo.c | 11 ++
7 files changed, 285 insertions(+), 115 deletions(-)
--
2.4.10
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