From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> The main motivation behind this series is to get the display to be stable on CHV. Some new memory power savings features got enabled on later steppings/BIOS versions which caused all kinds of display troubles with our current code. There are still a few known (at least known to me) display blink issues left after this series, but those have something to do with the PHY, and I'll post another series to address them. Vidya Srinivas (1): drm/i915: Program PFI credits for VLV Ville Syrjälä (11): drm/i915: Reduce CHV DDL multiplier to 16/8 drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines drm/i915: Simplify VLV drain latency computation drm/i915: Hide VLV DDL precision handling drm/i915: Reorganize VLV DDL setup drm/i915: Pass plane to vlv_compute_drain_latency() drm/i915: Read out display FIFO size on VLV/CHV drm/i915: Make sure PND deadline mode is enabled on VLV/CHV drm/i915: Rewrite VLV/CHV watermark code drm/i915: Support maxfifo with two planes on CHV drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV drivers/gpu/drm/i915/i915_drv.h | 20 ++ drivers/gpu/drm/i915/i915_reg.h | 32 ++- drivers/gpu/drm/i915/intel_display.c | 33 +++ drivers/gpu/drm/i915/intel_pm.c | 537 ++++++++++++++++++++--------------- 4 files changed, 385 insertions(+), 237 deletions(-) -- 2.0.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
