Ping. If someone can confirm it. I can submit a patch, but I'm concerned about introducing new register bit needs some internal process.... -----Original Message----- From: Intel-gfx [mailto:intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of Wang, Zhi A Sent: Monday, February 09, 2015 11:05 PM To: Intel-gfx@xxxxxxxxxxxxxxxxxxxxx Subject: About CTX_CONTEXT_CONTROL initialization in populate_lr_context() intel_lrc.c Hi Gurus: Forgive my junior HW knowledge, I just found that in execlist context initialization function populate_lr_context(), this line: reg_state[CTX_CONTEXT_CONTROL+1] = _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); It seems the "Inhibit Synchronous Context Switch" bit is not set here, so when HW is trying to wait some events, e.g. semaphore, according to Bspec, per my basic understanding, it will switch out current context with some reason bit set. Here comes my question, I think if this situation happen, should i915 remember this context and try to re-schedule it in a proper time, e.g. before submitting a new context until the context_completed bit in CSB is set? I don't find a register that will remember the context switched out by waiting event, so I think it should be i915 to handle this situation or just set "Inhibit Synchronous Context Switch" bit here?... Thanks, Zhi. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
