On 14.11.2013 09:21, Daniel Vetter wrote:
On gen2/3 the fence registers make a tile range look linear to both the gpu and the cpu. On gen4+ the fence registers are only for access with the cpu, and everything else needs to take tiling into account explicitly (and there are bits in the registers to tell the gpu that something is tiled). See the various functions with fence in their name in i915_gem.c for how this is set up/tracked.
Hmm. Probably I still don't quite understand. Memory is shared between CPU and GPU, so why does a memory write or read by the CPU depend on the GPU programming? The GPU is, after all, not a MMU that manipulates the address bus of the CPU (or does it?)
If the start address of the display is altered, are the tiles always relative to this start, i.e. at the same absolute display position, or do they move on screen, i.e. are at the same absolute memory position? Would it possibly make sense to check whether modifying the fence registers avoids the problem because then the tiles move, and probably stay aligned to 16-byte (or 32-byte) boundaries?
Greetings, Thomas _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
