Hi Daniel, dear intel-experts,
please find a revised patch attached that addresses the flicker with
panning on the i830 chipset. This patch has now been tested
on various screen layouts and seems to be quite reliable, i.e. I haven't
seen the flicker since.
Unfortunately, I have not been able to find a good workaround for the
same problem on a tiled framebuffer, the pattern there, i.e. when
the flicker appears, is quite irregular, and it is unclear how to
address it. The situation is even worse for 8bit/pixel framebuffers where,
for some panning positions, the display remains completely blank. It
flickers once or twice, then gets a hick-up, and then stays off.
The patch is currently only active on the i830, and only on pipelines
using the VGA or DVO output. Strangely enough, LVDS does not
seem to be affected, so maybe it is some memory/prefetch related
problem. I also checked the debug output, though I found no
suspicious activity while the screen flickers or is off. For a linear
framebuffer, it seems to be enough to position the start of the
pipeline ahead of the desired position, wait one vertical blank, and
then adjust it to the correct position. For tiling or 8bit modes,
this does not work.
Sorry if the formatting is off. This is just what emacs left me with.
Please feel free to reformat as you prefer.
As a related question: Is there possibly a command line tool that would
allow me to modify the intel chipset registers on the fly without going
through a kernel recompile? It would make some experiments just so much
simpler.
Greetings,
Thomas
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e5eb11d..e98298f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2087,8 +2087,44 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE(DSPLINOFF(plane), linear_offset);
- } else
- I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
+ } else if (INTEL_INFO(dev)->gen == 2 && IS_I830(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+ unsigned long planeadr = i915_gem_obj_ggtt_offset(obj) + linear_offset;
+ DRM_DEBUG_KMS("Plane address is 0x%lx",planeadr);
+ // I830 panning flicker work around. Only for non-LVDS output, only for i830.
+ if (obj->tiling_mode != I915_TILING_NONE) {
+ if ((planeadr & 0x40)) {
+ DRM_DEBUG_KMS("Detected potential flicker in tiling mode");
+ DRM_DEBUG_KMS("No workaround available");
+ DRM_DEBUG_KMS("Use a linear frame buffer");
+ }
+ } else {
+ switch (fb->pixel_format) {
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_ARGB1555:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ {
+ unsigned long int oldadr = I915_READ(DSPADDR(plane));
+ if (((oldadr ^ planeadr) & 0x40) && (planeadr & 0xc0) == 0xc0) {
+ DRM_DEBUG_KMS("Detected potential flicker in linear mode");
+ I915_WRITE(DSPADDR(plane), planeadr & (~(0x80)));
+ POSTING_READ(reg);
+ intel_wait_for_vblank(dev,intel_crtc->pipe);
+ }
+ }
+ break;
+ default:
+ DRM_DEBUG_KMS("No flicker workaround available\n");
+ break;
+ }
+ }
+ I915_WRITE(DSPADDR(plane), planeadr);
+ } else {
+ I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
+ }
POSTING_READ(reg);
return 0;
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