On Thu, Nov 14, 2013 at 8:14 AM, Thomas Richter <thor@xxxxxxxxxxxxxxxxx> wrote: > Are you *really sure* GEN2 does have tiling? Or could it be that this bit is > used for something else and probably turns on some weird powersaving feature > that creates some mischief with the FIFO? After all, a tile cannot always be > 128 pixels long independent of the display organization (i.e. "pixel > format") *and* have the above formula correct? > > There is then at least something I must be missing. On gen2/3 the fence registers make a tile range look linear to both the gpu and the cpu. On gen4+ the fence registers are only for access with the cpu, and everything else needs to take tiling into account explicitly (and there are bits in the registers to tell the gpu that something is tiled). See the various functions with fence in their name in i915_gem.c for how this is set up/tracked. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
