Am 11.11.2013 16:43, schrieb Daniel Vetter:
Oh, that's really interesting. gen2 has a unified display fifo on
machines that support 2 outputs. DSPARB tells the hw how to exactly
split this up between the two pipes. There are two bit ranges of
interest here:
/* snip */
Hmm, why I understand *that* it does make a difference, I do not
understand the details.
By a unified display fifo do you mean that the display output has an
internal buffer memory (the fifo) which
basically feeds the the DVOs or the LVDS with memory, which comes via
DMA into the fifo. Is that right?
By "split", do you mean that a fixed amount of bytes (or rather, lines
as in multiples of 16 bytes) are allocated for each
participating pipe?
Simply enlarging the fifo does not help (i.e. writing a larger value
into the register). Just the positions where I get the flicker change,
but the problem does not go away. So whatever needs to be done is to
adjust this register according to the alignment of the base address of
the corresponding DMA engine that feeds the pipe.
What we'd need to do here is to update this register when switching
the number of active display pipes in the ->modeset_global_resources
hook. We also need to make sure we have updated watermark values set
up already, before rewriting the value of DSPARB (since the watermarks
depend upon the size of the fifo).
For I start I'd go with splitting the fifo according to the display
clock between plane A and B and giving nothing to plane C. We don't
have any code to use plane C so giving everything to just A and B is
better.
By that you mean "BEND = maximum" and "AEND" in between? That does not
seem to be sufficient. It needs to be modified according to the buffer
alignment, and sometimes smaller values work, sometimes larger ones.
Greetings,
Thomas
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