On Mon, Nov 11, 2013 at 4:33 PM, Thomas Richter <thor@xxxxxxxxxxxxxxxxx> wrote: > Now, how much is known about the register DSPARB, found at offset 0x70030? > > Because, if I just feed this register with "correct" values (for whatever > "correct" means), I do get a stable image > on pipe A and pipe B. I haven't found out what "correct" is, precisely, but > there is something I can do here. > By default, on my setup, the value here is 0x17e5f, but depending on the > scroll position, 0x17e51, 0x17e61, 0x17e6f > or 0x17e63 create stable images. So there is at least some way how to get > the image right, though I don't quite > understand the mechanics yet. > > BTW, now that I looked at intel_regs_dump: When the screen is flickering, I > do get "pipe A underruns". I tried working > with the watermark registers, but all I can get is a crashed GPU or a ripped > display, so this is not quite the right approach. > DSPARB seems to be the best trick so far, even though I don't quite get how > it works. Oh, that's really interesting. gen2 has a unified display fifo on machines that support 2 outputs. DSPARB tells the hw how to exactly split this up between the two pipes. There are two bit ranges of interest here: bits0-8: "AEND. This field selects one of the splits between two of the three portions of the display RAM allocated between display plane A, plane B, and display plane C. This field can only be programmed when one of the two pipes is disabled. When it is written. It takes effect on the next VBLANK for whichever pipe is currently active. The control granularity is 16-bytes. The total size of the Almador-M RAM is 288*16 bytes. The total size of the Montara-GM RAM is 256*16 bytes." bits 9-18: "BEND. This field selects one of the split between the two of the three portions of the display RAM allocated between display planes A, B, and C. This field can only be programmed when one of the two display pipes is disabled. It takes effect on the next VBLANK for whichever pipe is currently active. It must be programmed to a number larger than the value in AEND. The control granularity is 16-bytes and the total size of the Almador-M RAM is 288*16 bytes and the Montara-GM RAM is 256*16 bytes." Almador-M is i830M, Montara-GM is i855GM. Other gen2 chips have a different meaning for this register. What we'd need to do here is to update this register when switching the number of active display pipes in the ->modeset_global_resources hook. We also need to make sure we have updated watermark values set up already, before rewriting the value of DSPARB (since the watermarks depend upon the size of the fifo). For I start I'd go with splitting the fifo according to the display clock between plane A and B and giving nothing to plane C. We don't have any code to use plane C so giving everything to just A and B is better. I hope this helps you in your endeavor. Otherwise feel free to ping me on irc or mail. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
