This series provides some of the initial enablement patches for two upcoming discrete GPUs: * XeHP SDV: Xe_HP (version 12.50) graphics IP, no display IP * DG2: Xe_HPG (version 12.55) graphics IP, Xe_LPD (version 13) display IP Both platforms will need additional enablement patches beyond what's present in this series before they're truly usable, including various LMEM and GuC work that's already happening separately. The new features/functionality that these platforms bring (such as multi-tile support, dedicated compute engines, etc.) may be referenced in passing in some of these patches but will be fully enabled in future series. v2: - General rebase and incorporation of r-b's. - Re-order intel_gt_info and intel_device_info structures to eliminate some unnecessary padding after the size change of intel_engine_mask_t. (Tvrtko) - Use 'intel_step' mechanisms for revid->stepping mapping. (Jani) - Drop the DSC patches for now; they need some rework. (Jani) v3: - About 20 of the patches have landed upstream now. Rebase and resend the rest. Some of these are already reviewed, but have dependencies on other unreviewed patches (e.g., the new engine definitions, the initial SNPS PHY support, etc.). Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> Cc: James Ausmus <james.ausmus@xxxxxxxxx> Akeem G Abodunrin (1): drm/i915/dg2: Add new LRI reg offsets Animesh Manna (1): drm/i915/dg2: Update to bigjoiner path Ankit Nautiyal (1): drm/i915/dg2: Configure PCON in DP pre-enable path Daniele Ceraolo Spurio (1): drm/i915/xehp: handle new steering options Gwan-gyeong Mun (1): drm/i915/dg2: Update lane disable power state during PSR John Harrison (3): drm/i915/xehp: Extra media engines - Part 1 (engine definitions) drm/i915/xehp: Extra media engines - Part 2 (interrupts) drm/i915/xehp: Extra media engines - Part 3 (reset) Lucas De Marchi (2): drm/i915/xehpsdv: Define MOCS table for XeHP SDV drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper (18): drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP() drm/i915/xehp: Xe_HP forcewake support drm/i915/xehp: Loop over all gslices for INSTDONE processing drm/i915/xehpsdv: Add maximum sseu limits drm/i915/xehpsdv: Define steering tables drm/i915/xehpsdv: Read correct RP_STATE_CAP register drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV drm/i915/dg2: Add forcewake table drm/i915/dg2: Update LNCF steering ranges drm/i915/dg2: Add SQIDI steering drm/i915/dg2: Maintain backward-compatible nested batch behavior drm/i915/dg2: Report INSTDONE_GEOM values in error state drm/i915/dg2: Define MOCS table for DG2 drm/i915/dg2: Add MPLLB programming for SNPS PHY drm/i915/dg2: Add MPLLB programming for HDMI drm/i915/dg2: Add vswing programming for SNPS phys drm/i915/dg2: Update modeset sequences drm/i915/dg2: Wait for SNPS PHY calibration during display init Matthew Auld (1): drm/i915/xehp: Changes to ss/eu definitions Stuart Summers (1): drm/i915/xehpsdv: Add compute DSS type drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 161 +++- drivers/gpu/drm/i915/display/intel_display.c | 51 ++ .../drm/i915/display/intel_display_power.c | 5 + .../drm/i915/display/intel_display_types.h | 17 +- drivers/gpu/drm/i915/display/intel_dpll.c | 12 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 11 + drivers/gpu/drm/i915/display/intel_psr.c | 7 + drivers/gpu/drm/i915/display/intel_snps_phy.c | 862 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_snps_phy.h | 35 + drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 99 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 +- .../drm/i915/gt/intel_execlists_submission.c | 4 + drivers/gpu/drm/i915/gt/intel_gt.c | 66 +- drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 12 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 85 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 66 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 + drivers/gpu/drm/i915/gt/intel_reset.c | 6 + drivers/gpu/drm/i915/gt/intel_rps.c | 19 +- drivers/gpu/drm/i915/gt/intel_rps.h | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 116 ++- drivers/gpu/drm/i915/gt/intel_sseu.h | 20 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 155 +++- drivers/gpu/drm/i915/i915_debugfs.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 7 +- drivers/gpu/drm/i915/i915_getparam.c | 6 +- drivers/gpu/drm/i915/i915_gpu_error.c | 36 +- drivers/gpu/drm/i915/i915_pci.c | 6 +- drivers/gpu/drm/i915/i915_reg.h | 100 +- drivers/gpu/drm/i915/intel_device_info.h | 4 +- drivers/gpu/drm/i915/intel_uncore.c | 367 ++++++-- drivers/gpu/drm/i915/intel_uncore.h | 14 +- drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + include/uapi/drm/i915_drm.h | 3 - 40 files changed, 2251 insertions(+), 174 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.c create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.h -- 2.25.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
