| Series: | Begin enabling Xe_HP SDV and DG2 platforms (rev6) |
| URL: | https://patchwork.freedesktop.org/series/92135/ |
| State: | success |
| Details: | https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20698/index.html |
CI Bug Log - changes from CI_DRM_10382 -> Patchwork_20698
Summary
SUCCESS
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20698/index.html
Known issues
Here are the changes found in Patchwork_20698 that come from known issues:
IGT changes
Issues hit
-
igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-tgl-1115g4: PASS -> DMESG-WARN (i915#1887)
-
igt@runner@aborted:
Possible fixes
- igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: DMESG-WARN (i915#3303) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Participating hosts (43 -> 36)
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adls-4 fi-ctg-p8600 bat-adls-3 fi-bdw-samus
Build changes
- Linux: CI_DRM_10382 -> Patchwork_20698
CI-20190529: 20190529
CI_DRM_10382: 03db07ede8eeeae5fa12cb07684084e531db377b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6149: 34ff2cf2bc352dce691593db803389fe0eb2be03 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20698: bcdeb7e1edf0bcaf0131923ff8fec88d6da379d2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bcdeb7e1edf0 drm/i915/dg2: Configure PCON in DP pre-enable path
76199f2888ef drm/i915/dg2: Update to bigjoiner path
aa3166a1e277 drm/i915/dg2: Update lane disable power state during PSR
e45963bba93a drm/i915/dg2: Wait for SNPS PHY calibration during display init
c17b50b62625 drm/i915/dg2: Update modeset sequences
b1efd88312b8 drm/i915/dg2: Add vswing programming for SNPS phys
ba80b83c84a9 drm/i915/dg2: Add MPLLB programming for HDMI
2f1319f28f47 drm/i915/dg2: Add MPLLB programming for SNPS PHY
a4f5ef996270 drm/i915/dg2: Define MOCS table for DG2
6a189a7ddf4d drm/i915/dg2: Report INSTDONE_GEOM values in error state
9542a06a5a35 drm/i915/dg2: Maintain backward-compatible nested batch behavior
e1706eba9559 drm/i915/dg2: Add new LRI reg offsets
f7b8d3a066bf drm/i915/dg2: Add SQIDI steering
134cfcfd9c84 drm/i915/dg2: Update LNCF steering ranges
1ace9a8d1b2a drm/i915/dg2: Add forcewake table
4057f5104c28 drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
da9489e90eda drm/i915/xehpsdv: Read correct RP_STATE_CAP register
83b0be478cb4 drm/i915/xehpsdv: factor out function to read RP_STATE_CAP
3def48fb4238 drm/i915/xehpsdv: Define MOCS table for XeHP SDV
0a73f890d107 drm/i915/xehpsdv: Define steering tables
278d359e56da drm/i915/xehpsdv: Add compute DSS type
94a690b2b730 drm/i915/xehpsdv: Add maximum sseu limits
456e57370fcd drm/i915/xehp: Changes to ss/eu definitions
21933a40845a drm/i915/xehp: Loop over all gslices for INSTDONE processing
70b1a7998cf4 drm/i915/xehp: handle new steering options
2b3f9bef9095 drm/i915/xehp: Xe_HP forcewake support
25bc3daa002b drm/i915/xehp: Extra media engines - Part 3 (reset)
3f65d319057d drm/i915/xehp: Extra media engines - Part 2 (interrupts)
42a1f6157116 drm/i915/xehp: Extra media engines - Part 1 (engine definitions)
f90c0193e566 drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP()
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