On Mon, Oct 12, 2020 at 02:29:47PM -0700, Lucas De Marchi wrote:
> TGL power wells can be re-used for DG1 with the exception of the fake
> power well for TC_COLD.
>
> v2: use logic to skip power wells while copying instead of duplicating
> the definition of TGL power wells (Matt Roper)
>
> Bspec: 49182
>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Anshuman Gupta <anshuman.gupta@xxxxxxxxx>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Much simpler now. :-)
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++++--
> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7437c7a79e5f..4934c89882b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4150,7 +4150,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> .name = "TC cold off",
> .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> .ops = &tgl_tc_cold_off_ops,
> - .id = DISP_PW_ID_NONE,
> + .id = TGL_DISP_PW_TC_COLD_OFF,
> },
> {
> .name = "AUX A",
> @@ -4634,7 +4634,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> * The enabling order will be from lower to higher indexed wells,
> * the disabling order is reversed.
> */
> - if (IS_ROCKETLAKE(dev_priv)) {
> + if (IS_DG1(dev_priv)) {
> + err = set_power_wells_mask(power_domains, tgl_power_wells,
> + BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
> + } else if (IS_ROCKETLAKE(dev_priv)) {
> err = set_power_wells(power_domains, rkl_power_wells);
> } else if (IS_GEN(dev_priv, 12)) {
> err = set_power_wells(power_domains, tgl_power_wells);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 824590c5401f..4aa0a09cf14f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -105,6 +105,7 @@ enum i915_power_well_id {
> CNL_DISP_PW_DDI_F_AUX,
> ICL_DISP_PW_3,
> SKL_DISP_DC_OFF,
> + TGL_DISP_PW_TC_COLD_OFF,
> };
>
> #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
> --
> 2.28.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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