v7: - Remove already applied patches and rebase the rest - Refactor DG1 power well handling to re-use table from TGL - Squash patch to add all the ports in a single patch - Use IS_DGFX() for DMC_DEBUG register move Aditya Swarup (4): drm/i915/display: allow to skip certain power wells drm/i915/dg1: Add DPLL macros for DG1 drm/i915/dg1: Add and setup DPLLs for DG1 drm/i915/dg1: Enable ports Anshuman Gupta (2): drm/i915/dg1: DG1 does not support DC6 drm/i915/dg1: Update DMC_DEBUG register Clinton A Taylor (1): drm/i915/dg1: invert HPD pins Lucas De Marchi (5): drm/i915/cnl: skip PW_DDI_F on certain skus drm/i915/dg1: Add DG1 power wells drm/i915/dg1: Enable DPLL for DG1 drm/i915/dg1: add hpd interrupt handling drm/i915/dg1: map/unmap pll clocks Matt Atwood (1): drm/i915/dg1: Load DMC Michel Thierry (1): drm/i915/dgfx: define llc and snooping behaviour Stuart Summers (1): drm/i915/dg1: Add initial DG1 workarounds drivers/gpu/drm/i915/display/intel_csr.c | 12 +- drivers/gpu/drm/i915/display/intel_ddi.c | 92 ++++++++++++++- drivers/gpu/drm/i915/display/intel_display.c | 33 +++++- .../drm/i915/display/intel_display_debugfs.c | 9 +- .../drm/i915/display/intel_display_power.c | 60 ++++++---- .../drm/i915/display/intel_display_power.h | 3 + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 54 +++++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++ drivers/gpu/drm/i915/display/intel_sprite.c | 4 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 111 ++++++++++++++---- drivers/gpu/drm/i915/i915_irq.c | 67 +++++++++-- drivers/gpu/drm/i915/i915_pci.c | 4 + drivers/gpu/drm/i915/i915_reg.h | 59 +++++++++- drivers/gpu/drm/i915/intel_pm.c | 39 ++++-- 14 files changed, 470 insertions(+), 94 deletions(-) -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
