== Series Details == Series: Introduce DG1 URL : https://patchwork.freedesktop.org/series/82594/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8623a162621b drm/i915/display: allow to skip certain power wells -:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well_descs' - possible side-effects? #64: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:4598: +#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \ __set_power_wells(power_domains, __power_well_descs, \ + ARRAY_SIZE(__power_well_descs), skip_mask) total: 0 errors, 0 warnings, 1 checks, 50 lines checked 68df339f83b7 drm/i915/cnl: skip PW_DDI_F on certain skus d0032ba13005 drm/i915/dg1: Add DG1 power wells 427e81efb3e5 drm/i915/dg1: Add DPLL macros for DG1 4718a2b29fcc drm/i915/dg1: Add and setup DPLLs for DG1 bd28cc6aa15c drm/i915/dg1: Enable DPLL for DG1 b60e1f572176 drm/i915/dg1: add hpd interrupt handling 5c559e0d9227 drm/i915/dg1: invert HPD pins 4a9095a0b7bb drm/i915/dg1: map/unmap pll clocks -:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects? #244: FILE: drivers/gpu/drm/i915/i915_reg.h:10324: +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \ + ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2))) total: 0 errors, 0 warnings, 1 checks, 204 lines checked 2277e81c77bb drm/i915/dg1: Enable ports -:67: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Aditya Swarup <aditya.swarup@xxxxxxxxx>' total: 0 errors, 1 warnings, 0 checks, 32 lines checked 51a8641ffb98 drm/i915/dg1: Load DMC 5da8aa482e31 drm/i915/dg1: Add initial DG1 workarounds ad249d6324c6 drm/i915/dg1: DG1 does not support DC6 ef788aaa1608 drm/i915/dg1: Update DMC_DEBUG register 3200a254244e drm/i915/dgfx: define llc and snooping behaviour _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
