> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Sent: Thursday, September 17, 2020 6:08 PM
> To: Kulkarni, Vandita <vandita.kulkarni@xxxxxxxxx>
> Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Nikula, Jani <jani.nikula@xxxxxxxxx>; B S,
> Karthik <karthik.b.s@xxxxxxxxx>
> Subject: Re: [V12 4/4] drm/i915/dsi: Initiate fame request in cmd mode
>
> On Thu, Sep 17, 2020 at 11:56:44AM +0000, Kulkarni, Vandita wrote:
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > > Sent: Thursday, September 17, 2020 5:01 PM
> > > To: Kulkarni, Vandita <vandita.kulkarni@xxxxxxxxx>
> > > Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Nikula, Jani
> > > <jani.nikula@xxxxxxxxx>; B S, Karthik <karthik.b.s@xxxxxxxxx>
> > > Subject: Re: [V12 4/4] drm/i915/dsi: Initiate fame request in cmd
> > > mode
> > >
> > > On Wed, Sep 16, 2020 at 09:45:28PM +0530, Vandita Kulkarni wrote:
> > > > In TE Gate mode or TE NO_GATE mode on every flip we need to set
> > > > the frame update request bit.
> > > > After this bit is set transcoder hardware will automatically send
> > > > the frame data to the panel in case of TE NO_GATE mode, where it
> > > > sends after it receives the TE event in case of TE_GATE mode.
> > > > Once the frame data is sent to the panel, we see the frame counter
> > > > updating.
> > > >
> > > > v2: Use intel_de_read/write
> > > >
> > > > v3: remove the usage of private_flags
> > > >
> > > > v4: Use icl_dsi in func names if non static,
> > > > fix code formatting issues. (Jani)
> > > >
> > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
> > > > ---
> > > > drivers/gpu/drm/i915/display/icl_dsi.c | 26
> ++++++++++++++++++++
> > > > drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++
> > > > drivers/gpu/drm/i915/display/intel_dsi.h | 1 +
> > > > 3 files changed, 37 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > > index 2789020e20db..7d2abc7f6ba3 100644
> > > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > > @@ -205,6 +205,32 @@ static int dsi_send_pkt_payld(struct
> > > > intel_dsi_host
> > > *host,
> > > > return 0;
> > > > }
> > > >
> > > > +void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) {
> > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > + u32 tmp, flags;
> > > > + enum port port;
> > > > +
> > > > + flags = crtc->mode_flags;
> > > > +
> > > > + /*
> > > > + * case 1 also covers dual link
> > > > + * In case of dual link, frame update should be set on
> > > > + * DSI_0
> > > > + */
> > > > + if (flags & I915_MODE_FLAG_DSI_USE_TE0)
> > > > + port = PORT_A;
> > > > + else if (flags & I915_MODE_FLAG_DSI_USE_TE1)
> > > > + port = PORT_B;
> > > > + else
> > > > + return;
> > > > +
> > > > + tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
> > > > + tmp |= DSI_FRAME_UPDATE_REQUEST;
> > > > + intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); }
> > > > +
> > > > static void dsi_program_swing_and_deemphasis(struct intel_encoder
> > > > *encoder) {
> > > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > diff
> > > > --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index f862403388f6..11a20bf2255f 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -15621,6 +15621,16 @@ static void
> > > > intel_atomic_commit_tail(struct
> > > intel_atomic_state *state)
> > > > intel_set_cdclk_post_plane_update(state);
> > > > }
> > > >
> > > > + /*
> > > > + * Incase of mipi dsi command mode, we need to set frame update
> > > > + * for every commit
> > > > + */
> > > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> > > > + if (INTEL_GEN(dev_priv) >= 11 &&
> > > > + intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
> > > > + if (new_crtc_state->hw.active)
> > > > + icl_dsi_frame_update(new_crtc_state);
> > >
> > > If this is the thing that triggers the update then it should
> > > probably be called at the start of intel_pipe_update_end().
> >
> > I could move it to the end of intel_pipe_update_end, as we need TE to be
> enabled.
> > Because if the frame updates are gated then, the dsi controller will
> > not drive the vblank/ frame start to the display engine until it receives a TE
> in the presence of the frame update request.
> > And if we are in non gated mode then the dsi controller will
> > immediately drive the vblank/frame strart as soon as it receives the frame
> update request.
> >
> > So is it ok if I move it to the end of pipe_update_end..
>
> Sounds racy. Though TBH I can't tell whether the we'd still fire off the event
> at the right time if we kick the update at the start.
> Once kicked, is the frame upload going to wait for the TE and then try to stay
> ahead of the raster beam?
In case of TE gate mode it waits for TE before starting memory writes to the periphery.
So if we add this at the end of pipe_update, then we would have enabled the TE( as part of vblank enable call)
Then we do a frame update eg TE gate mode
We wait for 1 TE
Then we get another TE in which we can see that the frame counter is incremented.
And only now we would be able to send the Vblank event to the user space.
In the earlier TE we would not have sent the event as the frame counter couldn't have updated.
This is the workflow that is expected in case of TE gate mode.
I didn't get the race part, do you mean to say that the wait for TE duration need not be same always?
Because we could send the frame update any time?
Thanks,
Vandita
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
