On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Often we seem to detect an underrun right after modeset on gen2. > It seems to be a spurious detection (potentially the pipe is still > in a wonky state when we enable the planes). An extra vblank wait > seems to cure it. Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index a0d1057d75ee..f330054e64c5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7517,6 +7517,10 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, > intel_crtc_vblank_on(new_crtc_state); > > intel_encoders_enable(state, crtc); > + > + /* prevents spurious underruns */ > + if (IS_GEN(dev_priv, 2)) > + intel_wait_for_vblank(dev_priv, pipe); > } > > static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
