On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > The default fbc1 compression interval we use is 500 frames. That > translates to over 8 seconds typically. That's rather excessive > so let's drop it to 1 second. > > The hardware will not attempt recompression unless at least one > line has been modified, so a shorter compression interval should > not cause extra bandwidth use in the purely idle scenario. Of > course in the mostly idle case we are possibly going to recompress > a bit more. > > Should really try to find some kind of sweet spot to minimize > the energy usage... Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index b1eb6a2ecc43..6ee45d634cf6 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -727,8 +727,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, > cache->fb.modifier = fb->modifier; > cache->fb.stride = plane_state->color_plane[0].stride; > > - /* This value was pulled out of someone's hat */ > - cache->interval = 500; > + /* FBC1 compression interval: arbitrary choice of 1 second */ > + cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); > > cache->fence_y_offset = intel_plane_fence_y_offset(plane_state); > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
