On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > 'level' here means the highest level we can't use, so when checking > the fbc watermarks we need a -1 to get at the last enabled level. > > While at if refactor the code a bit to declutter > g4x_compute_pipe_wm(). > Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 33 +++++++++++++++++++++------------ > 1 file changed, 21 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 1e99b35f007e..1c92ebf64a34 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1344,6 +1344,23 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc, > } > } > > +static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state, > + int level) > +{ > + if (level < G4X_WM_LEVEL_SR) > + return false; > + > + if (level >= G4X_WM_LEVEL_SR && > + wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR)) > + return false; > + > + if (level >= G4X_WM_LEVEL_HPLL && > + wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL)) > + return false; > + > + return true; > +} > + > static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > @@ -1383,7 +1400,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > wm_state->wm.plane[plane_id] = raw->plane[plane_id]; > > level = G4X_WM_LEVEL_SR; > - > if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) > goto out; > > @@ -1395,7 +1411,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY); > > level = G4X_WM_LEVEL_HPLL; > - > if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) > goto out; > > @@ -1418,17 +1433,11 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > /* > * Determine if the FBC watermark(s) can be used. IF > * this isn't the case we prefer to disable the FBC > - ( watermark(s) rather than disable the SR/HPLL > - * level(s) entirely. > + * watermark(s) rather than disable the SR/HPLL > + * level(s) entirely. 'level-1' is the highest valid > + * level here. > */ > - wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL; > - > - if (level >= G4X_WM_LEVEL_SR && > - wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR)) > - wm_state->fbc_en = false; > - else if (level >= G4X_WM_LEVEL_HPLL && > - wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL)) > - wm_state->fbc_en = false; > + wm_state->fbc_en = g4x_compute_fbc_en(wm_state, level - 1); > > return 0; > } _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx