From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
I've checked a bunch of gen3/4 machines and all seem to have
consistent FSB frequency information in the CLKCFG register.
So let's read out hrawclk on all gen3+ machines. Although
apart from g4x/pnv aux/pps dividers we only really need this
for for i965g/gm cs timestamp increment.
The CLKCFG memory clock values seem less consistent but we
don't care about those here.
For posterity here's a list of CLKCFG vs. FSB dumps from
a bunch of machines (only missing lpt for a full set):
machine CLKCFG FSB
alv1 0x00001411 533
alv2 0x00000420 400 (Chris)
gdg1 0x20000022 800
gdg2 0x20000022 800
cst 0x00010043 666
blb 0x00002034 1333
pnv1 0x00000423 666
pnv2 0x00000433 666
965gm 0x00004342 800
946gz 0x00000022 800
965g 0x00000422 800
g35 0x00000430 1066
0x00000434 1333
ctg1 0x00644056 1066
ctg2 0x00644066 1066
elk1 0x00012420 1066
0x00012424 1333
0x00012436 1600
0x00012422 800
elk2 0x00012040 1066
For the mobile parts the chipset docs generally have these
documented to some degree (alv being the exception).
The two settings w/o any evidence are 0x5=400MHz on desktop
and 0x7=1333MHz on mobile. Though the mobile 1333MHz case
probably doesn't even exist since ctg is only documented
to go up to 1066MHz.
v2: Fix 400mhz readout for Chris's alv/celeron machine
Do a clean mobile vs. dekstop split since that's really
what seems to be going on
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx>
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 64 ++++++++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 3 +-
2 files changed, 42 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d57dfec7e9a5..9419a4724357 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2700,7 +2700,7 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv)
CCK_DISPLAY_REF_CLOCK_CONTROL);
}
-static int g4x_hrawclk(struct drm_i915_private *dev_priv)
+static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
{
u32 clkcfg;
@@ -2716,27 +2716,43 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
*/
clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
- /* ELK seems to redefine some of the values */
- if (IS_G45(dev_priv) && clkcfg == CLKCFG_FSB_1600_ALT)
- return 400000;
-
- switch (clkcfg) {
- case CLKCFG_FSB_400:
- return 100000;
- case CLKCFG_FSB_533:
- return 133333;
- case CLKCFG_FSB_667:
- return 166667;
- case CLKCFG_FSB_800:
- return 200000;
- case CLKCFG_FSB_1067:
- case CLKCFG_FSB_1067_ALT:
- return 266667;
- case CLKCFG_FSB_1333:
- case CLKCFG_FSB_1333_ALT:
- return 333333;
- default:
- return 133333;
+ if (IS_MOBILE(dev_priv)) {
+ switch (clkcfg) {
+ case CLKCFG_FSB_400:
+ return 100000;
+ case CLKCFG_FSB_533:
+ return 133333;
+ case CLKCFG_FSB_667:
+ return 166667;
+ case CLKCFG_FSB_800:
+ return 200000;
+ case CLKCFG_FSB_1067:
+ return 266667;
+ case CLKCFG_FSB_1333:
+ return 333333;
+ default:
+ MISSING_CASE(clkcfg);
+ return 133333;
+ }
+ } else {
+ switch (clkcfg) {
+ case CLKCFG_FSB_400_ALT:
+ return 100000;
+ case CLKCFG_FSB_533:
+ return 133333;
+ case CLKCFG_FSB_667:
+ return 166667;
+ case CLKCFG_FSB_800:
+ return 200000;
+ case CLKCFG_FSB_1067_ALT:
+ return 266667;
+ case CLKCFG_FSB_1333_ALT:
+ return 333333;
+ case CLKCFG_FSB_1600_ALT:
+ return 400000;
+ default:
+ return 133333;
+ }
}
}
@@ -2757,8 +2773,8 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
freq = pch_rawclk(dev_priv);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
freq = vlv_hrawclk(dev_priv);
- else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
- freq = g4x_hrawclk(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 3)
+ freq = i9xx_hrawclk(dev_priv);
else
/* no rawclk on other platforms, or no need to know it */
return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10187780e06c..f774ec2bcc99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3768,7 +3768,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/* Clocking configuration register */
#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
-#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
+#define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */
+#define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */
#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
--
2.26.2
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