Quoting Ville Syrjala (2020-05-14 13:38:38) > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > I've checked a bunch of gen3/4 machines and all seem to have > consistent FSB frequency information in the CLKCFG register. > So let's read out hrawclk on all gen3+ machines. Although > apart from g4x/pnv aux/pps dividers we only really need this > for for i965g/gm cs timestamp increment. > > The CLKCFG memory clock values seem less consistent but we > don't care about those here. > > For posterity here's a list of CLKCFG vs. FSB dumps from > a bunch of machines (only missing lpt for a full set): > machine CLKCFG FSB > alv1 0x00001411 533 > alv2 0x00000420 400 (Chris) > gdg1 0x20000022 800 > gdg2 0x20000022 800 > cst 0x00010043 666 > blb 0x00002034 1333 > pnv1 0x00000423 666 > pnv2 0x00000433 666 > 965gm 0x00004342 800 > 946gz 0x00000022 800 > 965g 0x00000422 800 > g35 0x00000430 1066 > 0x00000434 1333 > ctg1 0x00644056 1066 > ctg2 0x00644066 1066 > elk1 0x00012420 1066 > 0x00012424 1333 > 0x00012436 1600 > 0x00012422 800 > elk2 0x00012040 1066 > > For the mobile parts the chipset docs generally have these > documented to some degree (alv being the exception). > > The two settings w/o any evidence are 0x5=400MHz on desktop > and 0x7=1333MHz on mobile. Though the mobile 1333MHz case > probably doesn't even exist since ctg is only documented > to go up to 1066MHz. > > v2: Fix 400mhz readout for Chris's alv/celeron machine > Do a clean mobile vs. dekstop split since that's really > what seems to be going on > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Holds for all machines we are able to test, Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
