This is a new design proposal for DC3CO feature after discussing it with Ville and Imre. Unlike v6 this v7 version has a cleaner solution to froce the modeset at bootup by using a crtc_state state bool has_dc3co_exitline in order to configure and enable dc3co exitline. Suggestion and feedback are most welcome for this new design series. Anshuman Gupta (7): drm/i915/tgl: Add DC3CO required register and bits drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask drm/i915/tgl: Enable DC3CO state in "DC Off" power well drm/i915/tgl: Do modeset to enable and configure DC3CO exitline. drm/i915/tgl: DC3CO PSR2 helper drm/i915/tgl: switch between dc3co and dc5 based on display idleness drm/i915/tgl: Add DC3CO counter in i915_dmc_info drivers/gpu/drm/i915/display/intel_display.c | 7 + .../drm/i915/display/intel_display_power.c | 327 ++++++++++++++++-- .../drm/i915/display/intel_display_power.h | 16 + .../drm/i915/display/intel_display_types.h | 1 + .../gpu/drm/i915/display/intel_frontbuffer.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 51 +++ drivers/gpu/drm/i915/display/intel_psr.h | 2 + drivers/gpu/drm/i915/i915_debugfs.c | 6 + drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_params.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 10 + drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_pm.h | 2 + 13 files changed, 402 insertions(+), 30 deletions(-) -- 2.21.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
