On Tue, Jan 08, 2019 at 12:28:18PM +0000, Chris Wilson wrote: > Broadwater and the rest of gen4 do support being able to saving and > reloading context specific registers between contexts, providing isolation > of the basic GPU state (as programmable by userspace). This allows > userspace to assume that the GPU retains their state from one batch to the > next, minimising the amount of state it needs to reload and manually save > across batches. > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Cc: Kenneth Graunke <kenneth@xxxxxxxxxxxxx> Reading through the old mails on the subject this looks fine. Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index f89b8f199e3f..88109e0de051 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -219,6 +219,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) > return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, > PAGE_SIZE); > case 5: > + case 4: > /* > * There is a discrepancy here between the size reported > * by the register and the size of the context layout > @@ -235,7 +236,6 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) > cxt_size * 64, > cxt_size - 1); > return round_up(cxt_size * 64, PAGE_SIZE); > - case 4: > case 3: > case 2: > /* For the special day when i810 gets merged. */ > -- > 2.20.1 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
