Re: [RFC 2/7] drm/i915: Introduce runtime device info

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On Mon, Nov 12, 2018 at 05:12:37PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> 
> Idea of runtime device info is to contain all fields from the existing
> device info which are modified at runtime.
> 
> Initially we move there fields which are never set from the static
> tables ie.: num_rings, num_sprites, num_scalers,

If we accept that num_sprites[fused_off_pipe] can be non-zero
we could keep num_sprites and num_scalers in the static info.
I don't *think* we have any code that would rely on those being
zero.

> cs_timestamp_frequency_khz, sseu and has_pooled_eu.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c           | 27 +++---
>  drivers/gpu/drm/i915/i915_drv.c               | 17 ++--
>  drivers/gpu/drm/i915/i915_drv.h               |  3 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c         | 19 +++--
>  drivers/gpu/drm/i915/i915_gpu_error.h         |  1 +
>  drivers/gpu/drm/i915/i915_perf.c              |  5 +-
>  drivers/gpu/drm/i915/i915_query.c             |  2 +-
>  drivers/gpu/drm/i915/intel_device_info.c      | 82 +++++++++++--------
>  drivers/gpu/drm/i915/intel_device_info.h      | 42 ++++++----
>  drivers/gpu/drm/i915/intel_display.c          |  2 +-
>  drivers/gpu/drm/i915/intel_display.h          |  6 +-
>  drivers/gpu/drm/i915/intel_engine_cs.c        |  4 +-
>  drivers/gpu/drm/i915/intel_lrc.c              | 14 ++--
>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c       |  4 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.h       |  4 +-
>  drivers/gpu/drm/i915/intel_workarounds.c      |  6 +-
>  .../gpu/drm/i915/selftests/i915_gem_context.c |  6 +-
>  drivers/gpu/drm/i915/selftests/intel_lrc.c    |  4 +-
>  19 files changed, 144 insertions(+), 106 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 670db5073d70..1b8a3f203b92 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -48,7 +48,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
>  	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
>  
>  	intel_device_info_dump_flags(info, &p);
> -	intel_device_info_dump_runtime(info, &p);
> +	intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
>  	intel_driver_caps_print(&dev_priv->caps, &p);
>  
>  	kernel_param_lock(THIS_MODULE);
> @@ -3289,7 +3289,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
>  	seq_printf(m, "Global active requests: %d\n",
>  		   dev_priv->gt.active_requests);
>  	seq_printf(m, "CS timestamp frequency: %u kHz\n",
> -		   dev_priv->info.cs_timestamp_frequency_khz);
> +		   dev_priv->runtime_info.cs_timestamp_frequency_khz);
>  
>  	p = drm_seq_file_printer(m);
>  	for_each_engine(engine, dev_priv, id)
> @@ -3305,7 +3305,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused)
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>  	struct drm_printer p = drm_seq_file_printer(m);
>  
> -	intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);
> +	intel_device_info_dump_topology(&dev_priv->runtime_info.sseu, &p);
>  
>  	return 0;
>  }
> @@ -4341,7 +4341,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
>  				     struct sseu_dev_info *sseu)
>  {
>  #define SS_MAX 6
> -	const struct intel_device_info *info = INTEL_INFO(dev_priv);
> +	const struct intel_runtime_device_info *info = &dev_priv->runtime_info;
>  	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
>  	int s, ss;
>  
> @@ -4397,7 +4397,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>  				    struct sseu_dev_info *sseu)
>  {
>  #define SS_MAX 3
> -	const struct intel_device_info *info = INTEL_INFO(dev_priv);
> +	const struct intel_runtime_device_info *info = &dev_priv->runtime_info;
>  	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
>  	int s, ss;
>  
> @@ -4424,8 +4424,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>  		sseu->slice_mask |= BIT(s);
>  
>  		if (IS_GEN9_BC(dev_priv))
> -			sseu->subslice_mask[s] =
> -				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
> +			sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
>  
>  		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
>  			unsigned int eu_cnt;
> @@ -4459,10 +4458,10 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
>  
>  	if (sseu->slice_mask) {
>  		sseu->eu_per_subslice =
> -				INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
> +			dev_priv->runtime_info.sseu.eu_per_subslice;
>  		for (s = 0; s < fls(sseu->slice_mask); s++) {
>  			sseu->subslice_mask[s] =
> -				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
> +				dev_priv->runtime_info.sseu.subslice_mask[s];
>  		}
>  		sseu->eu_total = sseu->eu_per_subslice *
>  				 sseu_subslice_total(sseu);
> @@ -4470,7 +4469,7 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
>  		/* subtract fused off EU(s) from enabled slice(s) */
>  		for (s = 0; s < fls(sseu->slice_mask); s++) {
>  			u8 subslice_7eu =
> -				INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
> +				dev_priv->runtime_info.sseu.subslice_7eu[s];
>  
>  			sseu->eu_total -= hweight8(subslice_7eu);
>  		}
> @@ -4523,14 +4522,14 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>  		return -ENODEV;
>  
>  	seq_puts(m, "SSEU Device Info\n");
> -	i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
> +	i915_print_sseu_info(m, true, &dev_priv->runtime_info.sseu);
>  
>  	seq_puts(m, "SSEU Device Status\n");
>  	memset(&sseu, 0, sizeof(sseu));
> -	sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices;
> -	sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices;
> +	sseu.max_slices = dev_priv->runtime_info.sseu.max_slices;
> +	sseu.max_subslices = dev_priv->runtime_info.sseu.max_subslices;
>  	sseu.max_eus_per_subslice =
> -		INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
> +		dev_priv->runtime_info.sseu.max_eus_per_subslice;
>  
>  	intel_runtime_pm_get(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b1d23c73c147..9cfd5b145248 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -357,12 +357,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  		value = i915_cmd_parser_get_version(dev_priv);
>  		break;
>  	case I915_PARAM_SUBSLICE_TOTAL:
> -		value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
> +		value = sseu_subslice_total(&dev_priv->runtime_info.sseu);
>  		if (!value)
>  			return -ENODEV;
>  		break;
>  	case I915_PARAM_EU_TOTAL:
> -		value = INTEL_INFO(dev_priv)->sseu.eu_total;
> +		value = dev_priv->runtime_info.sseu.eu_total;
>  		if (!value)
>  			return -ENODEV;
>  		break;
> @@ -379,7 +379,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  		value = HAS_POOLED_EU(dev_priv);
>  		break;
>  	case I915_PARAM_MIN_EU_IN_POOL:
> -		value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> +		value = dev_priv->runtime_info.sseu.min_eu_in_pool;
>  		break;
>  	case I915_PARAM_HUC_STATUS:
>  		value = intel_huc_check_status(&dev_priv->huc);
> @@ -429,17 +429,18 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  		value = intel_engines_has_context_isolation(dev_priv);
>  		break;
>  	case I915_PARAM_SLICE_MASK:
> -		value = INTEL_INFO(dev_priv)->sseu.slice_mask;
> +		value = dev_priv->runtime_info.sseu.slice_mask;
>  		if (!value)
>  			return -ENODEV;
>  		break;
>  	case I915_PARAM_SUBSLICE_MASK:
> -		value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
> +		value = dev_priv->runtime_info.sseu.subslice_mask[0];
>  		if (!value)
>  			return -ENODEV;
>  		break;
>  	case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
> -		value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
> +		value = 1000 *
> +			dev_priv->runtime_info.cs_timestamp_frequency_khz;
>  		break;
>  	case I915_PARAM_MMAP_GTT_COHERENT:
>  		value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
> @@ -1372,7 +1373,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>  	if (i915_inject_load_failure())
>  		return -ENODEV;
>  
> -	intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
> +	intel_device_info_runtime_init(dev_priv);
>  
>  	if (HAS_PPGTT(dev_priv)) {
>  		if (intel_vgpu_active(dev_priv) &&
> @@ -1620,7 +1621,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
>  		struct drm_printer p = drm_debug_printer("i915 device info:");
>  
>  		intel_device_info_dump(&dev_priv->info, &p);
> -		intel_device_info_dump_runtime(&dev_priv->info, &p);
> +		intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
>  	}
>  
>  	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 08d25aa480f7..f677a9936d33 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1589,6 +1589,7 @@ struct drm_i915_private {
>  	struct kmem_cache *priorities;
>  
>  	const struct intel_device_info info;
> +	struct intel_runtime_device_info runtime_info;
>  	struct intel_driver_caps caps;
>  
>  	/**
> @@ -2663,7 +2664,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  #define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission()
>  #define USES_HUC(dev_priv)		intel_uc_is_using_huc()
>  
> -#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
> +#define HAS_POOLED_EU(dev_priv)	((dev_priv)->runtime_info.has_pooled_eu)
>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff80
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index c8d8f79688a8..3e872bb1f00a 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -589,15 +589,18 @@ static void print_error_obj(struct drm_i915_error_state_buf *m,
>  	err_puts(m, "\n");
>  }
>  
> -static void err_print_capabilities(struct drm_i915_error_state_buf *m,
> -				   const struct intel_device_info *info,
> -				   const struct intel_driver_caps *caps)
> +static void
> +err_print_capabilities(struct drm_i915_error_state_buf *m,
> +		       const struct intel_device_info *info,
> +		       const struct intel_runtime_device_info *runtime_info,
> +		       const struct intel_driver_caps *caps)
>  {
>  	struct drm_printer p = i915_error_printer(m);
>  
>  	intel_device_info_dump_flags(info, &p);
> +	intel_device_info_dump_runtime(runtime_info, &p);
>  	intel_driver_caps_print(caps, &p);
> -	intel_device_info_dump_topology(&info->sseu, &p);
> +	intel_device_info_dump_topology(&runtime_info->sseu, &p);
>  }
>  
>  static void err_print_params(struct drm_i915_error_state_buf *m,
> @@ -829,7 +832,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  	if (error->display)
>  		intel_display_print_error_state(m, error->display);
>  
> -	err_print_capabilities(m, &error->device_info, &error->driver_caps);
> +	err_print_capabilities(m,
> +			       &error->device_info,
> +			       &error->runtime_device_info,
> +			       &error->driver_caps);
>  	err_print_params(m, &error->params);
>  	err_print_uc(m, &error->uc);
>  
> @@ -1751,6 +1757,9 @@ static void capture_gen_state(struct i915_gpu_state *error)
>  	memcpy(&error->device_info,
>  	       INTEL_INFO(i915),
>  	       sizeof(error->device_info));
> +	memcpy(&error->runtime_device_info,
> +	       &i915->runtime_info,
> +	       sizeof(error->runtime_device_info));
>  	error->driver_caps = i915->caps;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
> index 8710fb18ed74..ede9aa5ae1a2 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.h
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h
> @@ -45,6 +45,7 @@ struct i915_gpu_state {
>  	u32 reset_count;
>  	u32 suspend_count;
>  	struct intel_device_info device_info;
> +	struct intel_runtime_device_info runtime_device_info;
>  	struct intel_driver_caps driver_caps;
>  	struct i915_params params;
>  
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2c2b63be7a6c..9054237251c3 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2646,7 +2646,8 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
>  static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
>  {
>  	return div64_u64(1000000000ULL * (2ULL << exponent),
> -			 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz);
> +			 1000ULL *
> +			 dev_priv->runtime_info.cs_timestamp_frequency_khz);
>  }
>  
>  static int
> @@ -3505,7 +3506,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>  		spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
>  
>  		oa_sample_rate_hard_limit = 1000 *
> -			(INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
> +			(dev_priv->runtime_info.cs_timestamp_frequency_khz / 2);
>  		dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
>  
>  		mutex_init(&dev_priv->perf.metrics_lock);
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 6fc4b8eeab42..6b2c6e6873d3 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -13,7 +13,7 @@
>  static int query_topology_info(struct drm_i915_private *dev_priv,
>  			       struct drm_i915_query_item *query_item)
>  {
> -	const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
> +	const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
>  	struct drm_i915_query_topology_info topo;
>  	u32 slice_length, subslice_length, eu_length, total_length;
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 89ed3a84a4fa..8385767aaf08 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -79,6 +79,15 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
>  #undef PRINT_FLAG
>  }
>  
> +void
> +intel_runtime_device_info_dump_flags(const struct intel_runtime_device_info *info,
> +				     struct drm_printer *p)
> +{
> +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
> +	DEV_RUNTIME_INFO_FOR_EACH_FLAG(PRINT_FLAG);
> +#undef PRINT_FLAG
> +}
> +
>  static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
>  {
>  	int s;
> @@ -100,13 +109,16 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
>  	drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
>  }
>  
> -void intel_device_info_dump_runtime(const struct intel_device_info *info,
> -				    struct drm_printer *p)
> +void
> +intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
> +			       struct drm_printer *p)
>  {
>  	sseu_dump(&info->sseu, p);
>  
>  	drm_printf(p, "CS timestamp frequency: %u kHz\n",
>  		   info->cs_timestamp_frequency_khz);
> +
> +	intel_runtime_device_info_dump_flags(info, p);
>  }
>  
>  void intel_device_info_dump(const struct intel_device_info *info,
> @@ -160,7 +172,7 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
>  
>  static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>  {
> -	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> +	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
>  	u8 s_en;
>  	u32 ss_en, ss_en_mask;
>  	u8 eu_en;
> @@ -199,7 +211,7 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>  
>  static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
>  {
> -	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> +	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
>  	const u32 fuse2 = I915_READ(GEN8_FUSE2);
>  	int s, ss;
>  	const int eu_mask = 0xff;
> @@ -276,7 +288,7 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
>  
>  static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
>  {
> -	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> +	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
>  	u32 fuse;
>  
>  	fuse = I915_READ(CHV_FUSE_GT);
> @@ -329,7 +341,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
>  
>  static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  {
> -	struct intel_device_info *info = mkwrite_device_info(dev_priv);
> +	struct intel_runtime_device_info *info = &dev_priv->runtime_info;
>  	struct sseu_dev_info *sseu = &info->sseu;
>  	int s, ss;
>  	u32 fuse2, eu_disable, subslice_mask;
> @@ -433,7 +445,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  
>  static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
>  {
> -	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> +	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
>  	int s, ss;
>  	u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
>  
> @@ -515,8 +527,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
>  
>  static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
>  {
> -	struct intel_device_info *info = mkwrite_device_info(dev_priv);
> -	struct sseu_dev_info *sseu = &info->sseu;
> +	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
>  	u32 fuse1;
>  	int s, ss;
>  
> @@ -524,9 +535,9 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
>  	 * There isn't a register to tell us how many slices/subslices. We
>  	 * work off the PCI-ids here.
>  	 */
> -	switch (info->gt) {
> +	switch (INTEL_INFO(dev_priv)->gt) {
>  	default:
> -		MISSING_CASE(info->gt);
> +		MISSING_CASE(INTEL_INFO(dev_priv)->gt);
>  		/* fall through */
>  	case 1:
>  		sseu->slice_mask = BIT(0);
> @@ -735,29 +746,30 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>   *   - after the PCH has been detected,
>   *   - before the first usage of the fields it can tweak.
>   */
> -void intel_device_info_runtime_init(struct intel_device_info *info)
> +void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv =
> -		container_of(info, struct drm_i915_private, info);
> +	struct intel_device_info *info = mkwrite_device_info(dev_priv);
> +	struct intel_runtime_device_info *runtime_info =
> +		&dev_priv->runtime_info;
>  	enum pipe pipe;
>  
>  	if (INTEL_GEN(dev_priv) >= 10) {
>  		for_each_pipe(dev_priv, pipe)
> -			info->num_scalers[pipe] = 2;
> +			runtime_info->num_scalers[pipe] = 2;
>  	} else if (IS_GEN9(dev_priv)) {
> -		info->num_scalers[PIPE_A] = 2;
> -		info->num_scalers[PIPE_B] = 2;
> -		info->num_scalers[PIPE_C] = 1;
> +		runtime_info->num_scalers[PIPE_A] = 2;
> +		runtime_info->num_scalers[PIPE_B] = 2;
> +		runtime_info->num_scalers[PIPE_C] = 1;
>  	}
>  
>  	BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
>  
>  	if (IS_GEN11(dev_priv))
>  		for_each_pipe(dev_priv, pipe)
> -			info->num_sprites[pipe] = 6;
> +			runtime_info->num_sprites[pipe] = 6;
>  	else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
>  		for_each_pipe(dev_priv, pipe)
> -			info->num_sprites[pipe] = 3;
> +			runtime_info->num_sprites[pipe] = 3;
>  	else if (IS_BROXTON(dev_priv)) {
>  		/*
>  		 * Skylake and Broxton currently don't expose the topmost plane as its
> @@ -768,15 +780,15 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  		 * down the line.
>  		 */
>  
> -		info->num_sprites[PIPE_A] = 2;
> -		info->num_sprites[PIPE_B] = 2;
> -		info->num_sprites[PIPE_C] = 1;
> +		runtime_info->num_sprites[PIPE_A] = 2;
> +		runtime_info->num_sprites[PIPE_B] = 2;
> +		runtime_info->num_sprites[PIPE_C] = 1;
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		for_each_pipe(dev_priv, pipe)
> -			info->num_sprites[pipe] = 2;
> +			runtime_info->num_sprites[pipe] = 2;
>  	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
>  		for_each_pipe(dev_priv, pipe)
> -			info->num_sprites[pipe] = 1;
> +			runtime_info->num_sprites[pipe] = 1;
>  	}
>  
>  	if (i915_modparams.disable_display) {
> @@ -860,7 +872,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  	}
>  
>  	/* Initialize command stream timestamp frequency */
> -	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
> +	runtime_info->cs_timestamp_frequency_khz =
> +		read_timestamp_frequency(dev_priv);
>  }
>  
>  void intel_driver_caps_print(const struct intel_driver_caps *caps,
> @@ -880,6 +893,8 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
>  void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_device_info *info = mkwrite_device_info(dev_priv);
> +	struct intel_runtime_device_info *runtime_info =
> +		&dev_priv->runtime_info;
>  	u32 media_fuse;
>  	unsigned int i;
>  
> @@ -888,27 +903,28 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
>  
>  	media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
>  
> -	info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> -	info->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> -			     GEN11_GT_VEBOX_DISABLE_SHIFT;
> +	runtime_info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> +	runtime_info->vebox_enable =
> +		(media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> +		GEN11_GT_VEBOX_DISABLE_SHIFT;
>  
> -	DRM_DEBUG_DRIVER("vdbox enable: %04x\n", info->vdbox_enable);
> +	DRM_DEBUG_DRIVER("vdbox enable: %04x\n", runtime_info->vdbox_enable);
>  	for (i = 0; i < I915_MAX_VCS; i++) {
>  		if (!HAS_ENGINE(dev_priv, _VCS(i)))
>  			continue;
>  
> -		if (!(BIT(i) & info->vdbox_enable)) {
> +		if (!(BIT(i) & runtime_info->vdbox_enable)) {
>  			info->ring_mask &= ~ENGINE_MASK(_VCS(i));
>  			DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
>  		}
>  	}
>  
> -	DRM_DEBUG_DRIVER("vebox enable: %04x\n", info->vebox_enable);
> +	DRM_DEBUG_DRIVER("vebox enable: %04x\n", runtime_info->vebox_enable);
>  	for (i = 0; i < I915_MAX_VECS; i++) {
>  		if (!HAS_ENGINE(dev_priv, _VECS(i)))
>  			continue;
>  
> -		if (!(BIT(i) & info->vebox_enable)) {
> +		if (!(BIT(i) & runtime_info->vebox_enable)) {
>  			info->ring_mask &= ~ENGINE_MASK(_VECS(i));
>  			DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
>  		}
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 88f97210dc49..83e19ac8e401 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -105,7 +105,6 @@ enum intel_ppgtt {
>  	func(has_logical_ring_elsq); \
>  	func(has_logical_ring_preemption); \
>  	func(has_overlay); \
> -	func(has_pooled_eu); \
>  	func(has_psr); \
>  	func(has_rc6); \
>  	func(has_rc6p); \
> @@ -154,8 +153,8 @@ struct intel_device_info {
>  
>  	u8 gen;
>  	u8 gt; /* GT number, 0 if undefined */
> -	u8 num_rings;
>  	intel_ring_mask_t ring_mask; /* Rings supported by the HW */
> +	u8 num_pipes;
>  
>  	enum intel_platform platform;
>  	u32 platform_mask;
> @@ -165,10 +164,6 @@ struct intel_device_info {
>  
>  	u32 display_mmio_offset;
>  
> -	u8 num_pipes;
> -	u8 num_sprites[I915_MAX_PIPES];
> -	u8 num_scalers[I915_MAX_PIPES];
> -
>  #define DEFINE_FLAG(name) u8 name:1
>  	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
>  #undef DEFINE_FLAG
> @@ -179,19 +174,33 @@ struct intel_device_info {
>  	int trans_offsets[I915_MAX_TRANSCODERS];
>  	int cursor_offsets[I915_MAX_PIPES];
>  
> -	/* Slice/subslice/EU info */
> -	struct sseu_dev_info sseu;
> +	struct color_luts {
> +		u16 degamma_lut_size;
> +		u16 gamma_lut_size;
> +	} color;
> +};
>  
> -	u32 cs_timestamp_frequency_khz;
> +#define DEV_RUNTIME_INFO_FOR_EACH_FLAG(func) \
> +	func(has_pooled_eu); \
> +
> +struct intel_runtime_device_info {
> +	unsigned int num_rings;
> +
> +	u8 num_sprites[I915_MAX_PIPES];
> +	u8 num_scalers[I915_MAX_PIPES];
>  
>  	/* Enabled (not fused off) media engine bitmasks. */
>  	u8 vdbox_enable;
>  	u8 vebox_enable;
>  
> -	struct color_luts {
> -		u16 degamma_lut_size;
> -		u16 gamma_lut_size;
> -	} color;
> +	u32 cs_timestamp_frequency_khz;
> +
> +	/* Slice/subslice/EU info */
> +	struct sseu_dev_info sseu;
> +
> +#define DEFINE_FLAG(name) u8 name:1
> +	DEV_RUNTIME_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> +#undef DEFINE_FLAG
>  };
>  
>  struct intel_driver_caps {
> @@ -248,13 +257,14 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
>  
>  const char *intel_platform_name(enum intel_platform platform);
>  
> -void intel_device_info_runtime_init(struct intel_device_info *info);
> +void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
>  void intel_device_info_dump(const struct intel_device_info *info,
>  			    struct drm_printer *p);
>  void intel_device_info_dump_flags(const struct intel_device_info *info,
>  				  struct drm_printer *p);
> -void intel_device_info_dump_runtime(const struct intel_device_info *info,
> -				    struct drm_printer *p);
> +void
> +intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
> +			       struct drm_printer *p);
>  void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
>  				     struct drm_printer *p);
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a7fa032310ae..cc30bf1172ad 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13892,7 +13892,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	int i;
>  
> -	crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
> +	crtc->num_scalers = dev_priv->runtime_info.num_scalers[crtc->pipe];
>  	if (!crtc->num_scalers)
>  		return;
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 5d50decbcbb5..607ddc4a0b11 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -105,7 +105,7 @@ enum i9xx_plane_id {
>  };
>  
>  #define plane_name(p) ((p) + 'A')
> -#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
> +#define sprite_name(p, s) ((p) * dev_priv->runtime_info.num_sprites[(p)] + (s) + 'A')
>  
>  /*
>   * Per-pipe plane identifier.
> @@ -294,12 +294,12 @@ struct intel_link_m_n {
>  
>  #define for_each_universal_plane(__dev_priv, __pipe, __p)		\
>  	for ((__p) = 0;							\
> -	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
> +	     (__p) < (__dev_priv)->runtime_info.num_sprites[(__pipe)] + 1;\
>  	     (__p)++)
>  
>  #define for_each_sprite(__dev_priv, __p, __s)				\
>  	for ((__s) = 0;							\
> -	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
> +	     (__s) < (__dev_priv)->runtime_info.num_sprites[(__p)];	\
>  	     (__s)++)
>  
>  #define for_each_port_masked(__port, __ports_mask) \
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bc147d9e6c92..b464ee0afb85 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -365,7 +365,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
>  		goto cleanup;
>  	}
>  
> -	device_info->num_rings = hweight32(mask);
> +	dev_priv->runtime_info.num_rings = hweight32(mask);
>  
>  	i915_check_and_clear_faults(dev_priv);
>  
> @@ -807,7 +807,7 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>  
>  u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
>  {
> -	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> +	const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
>  	u32 mcr_s_ss_select;
>  	u32 slice = fls(sseu->slice_mask);
>  	u32 subslice = fls(sseu->subslice_mask[slice]);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 08fd9b12e4d7..cc897f429635 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2343,9 +2343,9 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
>  static u32
>  make_rpcs(struct drm_i915_private *dev_priv)
>  {
> -	bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
> -	u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
> -	u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
> +	bool subslice_pg = dev_priv->runtime_info.sseu.has_subslice_pg;
> +	u8 slices = hweight8(dev_priv->runtime_info.sseu.slice_mask);
> +	u8 subslices = hweight8(dev_priv->runtime_info.sseu.subslice_mask[0]);
>  	u32 rpcs = 0;
>  
>  	/*
> @@ -2393,7 +2393,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
>  	 * must make an explicit request through RPCS for full
>  	 * enablement.
>  	*/
> -	if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
> +	if (dev_priv->runtime_info.sseu.has_slice_pg) {
>  		u32 mask, val = slices;
>  
>  		if (INTEL_GEN(dev_priv) >= 11) {
> @@ -2421,17 +2421,17 @@ make_rpcs(struct drm_i915_private *dev_priv)
>  		rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
>  	}
>  
> -	if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
> +	if (dev_priv->runtime_info.sseu.has_eu_pg) {
>  		u32 val;
>  
> -		val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
> +		val = dev_priv->runtime_info.sseu.eu_per_subslice <<
>  		      GEN8_RPCS_EU_MIN_SHIFT;
>  		GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
>  		val &= GEN8_RPCS_EU_MIN_MASK;
>  
>  		rpcs |= val;
>  
> -		val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
> +		val = dev_priv->runtime_info.sseu.eu_per_subslice <<
>  		      GEN8_RPCS_EU_MAX_SHIFT;
>  		GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
>  		val &= GEN8_RPCS_EU_MAX_MASK;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5df7f6e1ab5e..17270d8f1880 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7341,7 +7341,7 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
>  
>  	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
>  
> -	switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
> +	switch (dev_priv->runtime_info.sseu.eu_total) {
>  	case 8:
>  		/* (2 * 4) config */
>  		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 87eebc13c0d8..fccebf773461 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1566,7 +1566,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>  	const int num_rings =
>  		/* Use an extended w/a on gen7 if signalling from other rings */
>  		(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
> -		INTEL_INFO(i915)->num_rings - 1 :
> +		i915->runtime_info.num_rings - 1 :
>  		0;
>  	bool force_restore = false;
>  	int len;
> @@ -2231,7 +2231,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>  
>  		engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
>  
> -		num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
> +		num_rings = dev_priv->runtime_info.num_rings - 1;
>  		engine->emit_breadcrumb_sz += num_rings * 3;
>  		if (num_rings & 1)
>  			engine->emit_breadcrumb_sz++;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 8a2270b209b0..db2933d287b8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -94,11 +94,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
>  
>  #define instdone_slice_mask(dev_priv__) \
>  	(IS_GEN7(dev_priv__) ? \
> -	 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
> +	 1 : (dev_priv__)->runtime_info.sseu.slice_mask)
>  
>  #define instdone_subslice_mask(dev_priv__) \
>  	(IS_GEN7(dev_priv__) ? \
> -	 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
> +	 1 : (dev_priv__)->runtime_info.sseu.subslice_mask[0])
>  
>  #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
>  	for ((slice__) = 0, (subslice__) = 0; \
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index d7176213e3ce..110556d0934f 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -318,7 +318,7 @@ static int skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
>  		 * Only consider slices where one, and only one, subslice has 7
>  		 * EUs
>  		 */
> -		if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
> +		if (!is_power_of_2(dev_priv->runtime_info.sseu.subslice_7eu[i]))
>  			continue;
>  
>  		/*
> @@ -327,7 +327,7 @@ static int skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
>  		 *
>  		 * ->    0 <= ss <= 3;
>  		 */
> -		ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
> +		ss = ffs(dev_priv->runtime_info.sseu.subslice_7eu[i]) - 1;
>  		vals[i] = 3 - ss;
>  	}
>  
> @@ -732,7 +732,7 @@ static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  
>  static void wa_init_mcr(struct drm_i915_private *dev_priv)
>  {
> -	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> +	const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
>  	u32 mcr;
>  	u32 mcr_slice_subslice_mask;
>  
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index 7d82043aff10..4ee3fcff815a 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -627,7 +627,7 @@ static int igt_ctx_exec(void *arg)
>  		ncontexts++;
>  	}
>  	pr_info("Submitted %lu contexts (across %u engines), filling %lu dwords\n",
> -		ncontexts, INTEL_INFO(i915)->num_rings, ndwords);
> +		ncontexts, i915->runtime_info.num_rings, ndwords);
>  
>  	dw = 0;
>  	list_for_each_entry(obj, &objects, st_link) {
> @@ -732,7 +732,7 @@ static int igt_ctx_readonly(void *arg)
>  		}
>  	}
>  	pr_info("Submitted %lu dwords (across %u engines)\n",
> -		ndwords, INTEL_INFO(i915)->num_rings);
> +		ndwords, i915->runtime_info.num_rings);
>  
>  	dw = 0;
>  	list_for_each_entry(obj, &objects, st_link) {
> @@ -1064,7 +1064,7 @@ static int igt_vm_isolation(void *arg)
>  		count += this;
>  	}
>  	pr_info("Checked %lu scratch offsets across %d engines\n",
> -		count, INTEL_INFO(i915)->num_rings);
> +		count, i915->runtime_info.num_rings);
>  
>  out_rpm:
>  	intel_runtime_pm_put(i915);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c b/drivers/gpu/drm/i915/selftests/intel_lrc.c
> index 94fc0e5c8766..7237a2474805 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c
> @@ -719,7 +719,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
>  
>  	pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
>  		count, flags,
> -		INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext);
> +		smoke->i915->runtime_info.num_rings, smoke->ncontext);
>  	return 0;
>  }
>  
> @@ -747,7 +747,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags)
>  
>  	pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n",
>  		count, flags,
> -		INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext);
> +		smoke->i915->runtime_info.num_rings, smoke->ncontext);
>  	return 0;
>  }
>  
> -- 
> 2.19.1
> 
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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