Quoting jeff.mcgee@xxxxxxxxx (2018-03-16 18:30:59) > From: Jeff McGee <jeff.mcgee@xxxxxxxxx> > > Engine reset is fast. A context switch interrupt may be generated just > prior to the reset such that the top half handler is racing with reset > post-processing. The handler may set the irq_posted bit again after > the reset code has cleared it to start fresh. Then the re-enabled > tasklet will read the CSB head and tail from MMIO, which will be at > the hardware reset values of 0 and 7 respectively, given that no > actual CSB event has occurred since the reset. Mayhem then ensues as > the tasklet starts processing invalid CSB entries. > > We can handle this corner case without adding any new synchronization > between the irq top half and the reset work item. The tasklet can > just skip CSB processing if the tail is not sane. > > This patch is required to support the force preemption feature. Please note how this is handled currently, because this is not a new problem. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
