On 25/01/2018 14:32, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-01-25 14:26:53)
On 25/01/2018 13:57, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-01-25 13:33:32)
- if (engine && ((caps & engine->caps) != caps))
- return -EINVAL;
+ do {
+ engine = i915->engine[_VCS(instance)];
+ instance ^= 1;
+ vcs_instances--;
+ } while ((caps & engine->caps) != caps && vcs_instances > 0);
+
+ if ((caps & engine->caps) != caps)
+ return -EINVAL;
+
+ timeline = i915_gem_context_lookup_timeline_class(eb->ctx,
+ VIDEO_DECODE_CLASS);
+ spin_lock_irq(&timeline->lock);
+ prev_req = list_first_entry_or_null(&timeline->requests,
+ struct drm_i915_gem_request,
+ ctx_link);
+ spin_unlock_irq(&timeline->lock);
This isn't doing anything yet as we aren't using the timeline. The idea
is sound though, we need to rejig timelines to make them more flexible
so that we can combine them to use one per-queue. Ok.
I think it works - as far as I looked at the trace.pl HTML output it
seems to.
You are syncing against the oldest, not the previous (which would be
timeline->last_request).
Hey, my timeline my rules - see patch 7! :)
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
